At this year's DAC in San Francisco, EVE SA (Palaiseau, France) conducted a survey to determine preferences and prevalence of verification environments.
In this guest blog, Lauro Rizzatti, general manager of EVE USA, presents the survey findings, bearing strong promises for hardware-assisted verification vendors.
One of the benefits of exhibiting at the yearly Design Automation Conference is to take advantage of the opportunity to probe the design community on a series of issues at the heart of their daily tasks. This year was no different. At EVE, we asked everyone who stopped by our booth to answer a few questions about their current verification environment with a focus on hardware-assisted verification tools and their plans for the future.
Many of the answers were predictable. For example, Verilog topped the list of languages used for chip design, with SystemVerilog coming in at a distant second. Verilog came out on top again for testbench design. While SystemVerilog came next, it lagged behind Verilog by almost half.
When asked to rank the satisfaction level of their current verification flow, based on runtime performance, setup time, efficiency in catching corner cases and reusability, most were reasonably satisfied with a small minority complaining about all four criteria. In fact, about a quarter of the respondents were fairly content and 10 percent to 15 percent very pleased with all of the above.
The three major commercial simulators split the responses about evenly, with an edge in favor of VCS from Synopsys and Mentor Graphics' Modelsim, and not NC-Sim from Cadence. Surprisingly, a quarter claimed to own simulation farms with more than 200 seats, while 60 percent noted that they had less than 100 seats. It seems that farms with simulation seats between 100 and 200 are not that popular.
Things got intriguing when we asked survey respondents how they used their hardware-assisted verification environment. Almost half of the respondents wrote that they used this tool for simulation acceleration, and one-sixth each as in-circuit-emulation, stand-alone emulation and as transaction-based emulation. Using emulation as an accelerator shouldn't come as a huge surprise to anyone since it has always been used to supplement simulation, and now design sizes and complexity are overpowering simulation. All of these applications attest that emulation is a versatile tool.
More interesting was the ranking of six criteria in selecting the next hardware-assisted verification platform, including run-time performance, compilation performance, visibility into the design, in-circuit emulation (ICE), four-state support and price. Visibility into the design and compilation performance scored high, but run-time performance and price finished close behind.
Today's emulator is used in the design of some of the most intricate designs imaginable, from processors, digital multimedia, networking and storage to telecommunications, mobile communications and other sophisticated consumer electronics devices. Most respondents noted that they used hardware-assisted verification for application specific integrated circuit (ASIC) validation, though almost as many use it for hardware/software co-verification, or for overall system-on-chip (SoC) design, as well.