Since our business depends on understanding assertion usage, we have spent a lot of time examining the problems and we think we have our arms around the situation.
Here is a summary of what we have learned.
Assertion Based Verification (ABV) has proven to cut debug time in half and has been viewed as the technology having the most impact on reducing verification time and cost. SystemVerilog with ABV has been considered the evolving standard for the most complex chip designs.
Despite good promises, wide-scale use of ABV has not materialized because it is a difficult technology to implement and is perceived as marginally cost-effective. If it had been easy, everyone would have jumped on it by now.
Key to understanding the problem is the difference in the terms "Using Assertions" and "Assertion Based Verification."
. Using assertions is an ad hoc process dependent on the skill and desire of the individual designer or verification engineer to provide assertions as part of the functional verification process.
. ABV is a systematic methodology requiring the use of assertions in the functional verification flow.
Most surveys are about assertion use as opposed to ABV..... A big difference, and we believe terminology is a problem that confuses the issue.
The prevalent approach today is using assertions on an ad hoc basis by designers at the block level and verification engineers at the system level. Assertion use at the block level is more prevalent since a block level bug deep into the design cycle can result in a major schedule hit. Since designers are intimately familiar with the intent of the design and many are capable of coding simple 1 or 2 cycle SVAs and, they are more likely to create and add assertions. Since assertion use is at their discretion, they are added in-line as part of the design file without documentation.
At the system level, useful SVAs typically require a higher level of complexity than at the block level. Temporal properties are the norm and since the verification engineer cannot modify the design files, bind files are required. Creating and managing bind files is a labor intensive task. The SVA language learning curve can be extensive for complex temporal expressions and using assertions even on an ad hoc basis is sparse. Certainly, many companies have SVA coding experts that can be brought in for situations where the need for a complex temporal SVA is obvious. However, the broad base of verification engineers lacks the expertise to write this level of assertions.
Harry Foster, in a paper entitled 'Assertion-Based Verification: Industry Myths to Realities' defined the situation more bluntly. He declared: "It is a myth that ABV is a mainstream technology."
Howard L. Martin, President of Zocalo Tech, has over 30 years of experience in EDA sales and management specializing in early stage startups. He was one of the first salesmen when EDA emerged as a distinct market working for Daisy Systems. After the merger of ECAD and SDA to form Cadence he was Western Area Director. He has also held positions with Recal Redac, Quickturn and Aptix, and was a founder and president of SpeedGate, Inc.
Martin (email@example.com) has a BS in Aeronautical Engineering and MS in Physics from Texas A&M.