In this week's Guest Blog, Sanjiv Taneja, Vice President, Encounter Test, Cadence Design Systems, Inc., highlights the need to focus on Design for test (DFT) with a more holistic view of the economics of test.
Design for test (DFT) has not drawn the kind of attention that design for manufacturability (DFM) has received in recent years, but test is becoming significantly more difficult and expensive at nanometer process nodes. Test costs are escalating, adding to overall product costs, and the potential for yield loss due to test-related issues is rising. What's needed is a renewed focus on DFT with a more holistic view of the economics of test than we've had in the past.
Conventionally, test costs are evaluated in terms of capital costs and operating costs. The evaluation starts with the cost of the ATE equipment and considers what it costs to operate the equipment for a given period of time. The focus then shifts to optimizing throughput so as to minimize the time that any one IC spends on the tester. To do so, test engineers seek to provide maximum test coverage within a minimum data volume so results can be provided in the shortest possible time.
While these considerations are still important, the notion of "test cost" needs to take a much broader view given the advances in nanometer process technology, the increasing role of analog/mixed-signal circuitry, and the drive for low-power design. Cost evaluations must consider power, design/test integration, analog/mixed-signal test, the cost of escaped defects, and product yield learning. EDA technology needs to provide tangible ways of reducing costs in each of these areas.
Impact of power on yield and test cost
Low-power design is pervasive at nanometer process nodes. Most designers are concerned about functional power, not test power. But test power becomes an important issue when low-power design techniques such as clock gating, state retention flops and power shutoff are used. Power-aware DFT techniques are needed to overcome the limitations of traditional methods such as inadequate testing of the power management structures, inability to map to operational power modes, and excessive power dissipation in the test mode that do not take the design's power architecture into consideration.
The ability to map to a subset of operational power modes during manufacturing test is becoming increasingly vital in order to ensure a full structural test of all the low-power components. Power-aware test generation tools need to accurately model the behavior of the different power structures and power modes. This enables automatic test pattern generation (ATPG) to target faults within low-power structures such as isolation logic, level shifters, and state-retention flops.
Reducing power during test is key consideration because excessive switching can cause good dies to fail on the tester, therefore resulting in yield loss. One reason why ATPG patterns often cause a lot of switching activity is that typically only about 1-3 percent of the bits are "care about" bits. The other 97 percent are random. Power-aware ATPG helps avoid excessive switching caused by random bits, but it needs the smarts to concurrently optimize for power while avoiding an increase in test time that would drive up costs.
Design/test integration allows testing on low cost equipment
Test needs to be deeply integrated with the design implementation flow. In particular, synthesis tools should optimize not only for area, timing and power, but also for testability. Additionally, early DFT checking at the register-transfer level should identify and fix subtle coverage limiting issues such as X (unknown) sources, and produce higher compression ratios and higher test coverage, thereby making it possible for devices to fit on low-pin count, low cost testers. This reduces test data volume and test time.
On-chip compression logic is a DFT practice that can have a profound impact on design. Many nanometer chips use on-chip test pattern compression in order to reduce test data volume and reduce test costs. However, compression architectures can impact timing closure and routing congestion. Another example of design/test integration comes from scan chain ordering, which can impact scan wire length and ultimately timing closure.
What does all this have to do with economics?
Design/test integration directly impacts productivity and it impacts the ability to achieve manufacturing closure. Good integration can make it possible to achieve high test coverage in a single pass, without having to go back and tweak the design.