After 35 plus years of being in the semiconductor business, custom IC design still is an extremely interesting challenge.
Variation analysis is only useful if the designer can do fast, iterative analysis, while maintaining the same accuracy. This is what "variation-aware" custom IC design is about giving designers sufficient simulation and convergence speed to make it possible to examine design tradeoffs. In this way, instead of just doing verification, designers can proactively design-for-variation prior to tapeout without over-margining or under-designing.
What methods are available to the custom designer to ensure his design is optimal for the target process? I learned the hard way that to be adopted, variation-aware tools must keep existing custom IC design methods intact. To be efficient, these tools require Optimal Sampling algorithms, coupled with Design-Specific (DS) corners.
Optimal Sampling algorithms are a class of sampling algorithms that include techniques such as Design-of-Experiments and Optimal Spread Sampling. Optimal Sampling algorithms can be adaptive, in which the next round of samples are determined by results from previous samples via the appropriate analysis. Design-Specific corners are a small set of representative corners that simulate quickly and capture the bounds of the circuit's performance distribution performances against which the designer can perform rapid and accurate design iterations. The accuracy of the corners is crucial they must faithfully represent the bounds of the performances, either in the worst-case sense (as in PVT design), or in the statistical-tail sense (as in Monte Carlo design). Optimal Sampling is key to extracting such accurate corners.
Optimal Sampling and Design-Specific corners allow designers to scale their design approaches with exponentially worsening variation. They can achieve the same accuracy as Monte Carlo with orders of magnitude fewer samples, and extract design-specific statistical corners that capture random and environmental variation to improve design accuracy over generic PVT corners for rapid design iterations.
By incorporating optimal sampling and design-specific corner methods into variation-aware custom IC design, designers can avoid costly over-margining or under-designing, and avoid delaying project schedules. As a result, semiconductor companies will be able to more fully realize better performing, higher yielding, improved power and improved area designs results from smaller process nodes, while accelerating their aggressive project schedules.
I kept this discussion focused on traditional 2D structures. As we start to consider 3D structures, the complexity and variance will be even greater. This will continue to be a ripe field of exploration.
About the author:
Jim Hogan has worked in the semiconductor design and manufacturing industry for more than 35 years gaining experience as a senior executive in electronic design automation, semiconductor intellectual property, semiconductor equipment and fabrication companies.
Hogan currently is the managing partner of Vista Ventures LLC and is an active strategic consultant to public and private technology companies. Prior to Vista, Hogan was a general partner at Telos Venture Partners and senior vice president of business development at Artisan Components Inc., now part of ARM Holdings PLC. He held senior executive engineering, marketing and operational management positions at Cadence Design Systems, Inc., National Semiconductor Corporation and Phillips Semiconductor. At Cadence, he was an executive fellow, president of Cadence Japan, corporate vice president of marketing, and corporate vice president for field operations.
Hogan holds a B.A degree in mathematics, a B.S. degree in computer science and an M.B.A all from San Jose State University. He serves on the Board of Advisors at San Jose State's School of Engineering, and on the board of directors of several technology startups.