You hear it every day these days: Do more with less. Design more products faster. In effect, “do Moore’s Law” with less.
No doubt you’re familiar with some of the reasons for this:
. Our industry may have put the recession in the rear-view mirror, but product-development organizations are being kept lean and mean to manage costs.
. IC-development costs ($50-$100 million) are staggering and rising.
. Many remaining vertically integrated device manufacturers (IDMs) have sold off costly fabs to improve their balance sheets. They need new differentiation and are looking to more productive product-development groups for that differentiation.
. Venture capital (VC) investment in semiconductor companies is at a 10-year low.
For years, we’ve helped leading semiconductor R&D groups improve their development productivity. Today we’re launching a free trial product for EE Times readers that showcases some of the capability those R&D organizations use before they start their design projects.
IC Project Analyzer enables you to assess the complexity of a semiconductor project being planned and benchmark the execution assumptions of your project plan to determine schedule risk. Likewise, you can benchmark a recently completedor nearly completedproject to assess your team’s performance against the industry.
Our dataas well as surveys over the years from EE Timesreveal that most design projects slip schedulemany by more than a year. That means lost market opportunity and cost overruns. In large product-development organizations, schedule slip has a ripple effect, because resources tied up on one delayed project are prevented by being used on others.
Take IC Project Analyzer for a spinit will take just a few minutes.
First, enter your project datachip- and block-level datausing as much detail as possible. After you hit continue, up will pop a complexity rating that indicates where your project’s development complexity compares to the industry at large.
The next page allows you to describe your team’s experience level and to alter staffing profiles to fit your staffing situation.
The last pagedepending on whether you chose to determine schedule risk or benchmark a completed or nearly completed projectcompares your project’s development effort to industry norms for similar projects, say in wireless design or automotive.
The more you work with IC Project Analyzer, the more you can get a sense for the technology and staffing tradeoffs you might need to make on your current on future projects. And you make these decisions based on facts and data as continue to do Moore with less.
Let me know what you think at email@example.com.
About the author:
Brian Fuller is director, Communications and Community, at Numetrics Management Systems, Inc. (Cupertino, Calif.).
Brian Fuller has more than 25 years’ experience in journalism and communications, most recently as director of communications and community at Numetrics.
Before Numetrics, Brian spent 18 months at the high-tech PR consultancy Blanc & Otus in San Francisco. Prior to that, he spent 15 years at EE Times in various positions, including six as editor-in-chief. He began his career as a reporter for United Press International.