If the views of Greg Atwood of Micron Technology on phase-change memory (PCM) scalability are a measure of the quality of his paper, The evolution of phase-change memory, then its overall value is suspect.
Atwood writes: “Scalability is one of the major motivations for the development of PCM”. He relies on facts with respect to scalability that may have been true in the early history of PCM development, but no longer match the situation.
His argument that the scaling of the number of electrons stored in a flash memory can be compared to a material that can change its phase is naive.
A more realistic comparison would be with the means by which the phase change is achieved and the consequences that come with scaling. The power required to heat the PCM material to 600 degrees C (cherry red) requires current and the reset current scales with minimum lithographic dimensions. This is true at larger lithographic nodes when the initiating molten hotspot of the PCM is relatively well distanced from the surrounding electrodes and dielectric.
Current scaling continues with shrinking dimensions but current density (J) does not. The reason is the volume of material in which heat can be generated is decreasing as r3 while the cooling area is decreasing as r2. The spherical case is a good approximation.
From the literature and from consideration of published results, current densities of up to 2x10E8 A/sq-cm would be expected for devices with dimensions of from 5- to 20-nm.
Does Atwood suggest, as he makes his case for scaling, that current densities at the levels cited above, flowing in molten chalcogenide have no effect? Electro-migration must occur and change the composition in the direction of current flow. What, with scaling, will be the impact of that change on write/erase lifetime, elevated temperature data storage and other device parameters and reliability?
My examination of the published results, (including Samsung ), indicates that by increasing the length-to-diameter aspect ratio of constrained PCM structures, i.e thermal engineering, it is possible to make what appears to be some promising progress toward lower current densities with reducing lithographic dimensions. The result is PCM current densities of 1 to 3 x10E7 A/sq-cm for devices in the 40-nm range. However, this approach most likely incurs a process yield problem, and self-evident thermal considerations limit the value of this approach before the current density starts to increase again. The thermal benefit of making devices longer by moving the electrodes away from the active volume is limited.
The next PCM scalability problem that Atwood ignores is the effect of current density on the matrix isolation device. Tightly packed bipolar or MOS devices do not operate reliably at the current densities that will be required at PCM dimensions in the range 5 to 30 nm. Perhaps his claims for PCM scalability would appear to rest on the development of a new type of matrix isolation device. (For this, IBM has suggested in a recent paper  that the way forward would be an if-you-cannot-beat-them-join-them approach to electro-migration and use of ionic copper conduction in a matrix isolation threshold switch they have developed for 3-D PCM). Is this what Atwood meant by solid state disk drives?
I am tempted to suggest that in a highly constrained PCM cell it might be possible to create a situation where the electro-migration flux exactly balances the thermal back-diffusion flux. For the moment I will leave that to others.
In light of the above and your claims for scalability, what does “ready for prime time as a next-generation nonvolatile memory” actually mean? A more detailed explanation from Micron, your new employer, would be helpful with a product roadmap and time lines.
My view is there still is a lot more work to be done.
R. G. Neale London
Former editor-in-chief of Electronic Engineering
Co-author of Nonvolatile and reprogrammable, the read-mostly memory is here, by R.G.Neale, D.L.Nelson and Gordon E. Moore, Electronics, pp56-60, Sept. 28, 1970.
 Highly scalable on-axis confined cell structure for high density PRAM beyond 256Mb, S.L.Cho et al., Samsung, Symposium on VLSI Technology, 2005
 Highly-scalable novel access device based on mixed ionic electronic conduction (MIEC) materials for high density phase change memory (PCM) arrays, K. Gopalakrishnan et al., IBM Almaden Research Center, USA, Symposium on VLSI Technology, 2010.
ExDRAMer-When you say my number is lower, for example 6 to 10 times lower. If I multiply my numbers the range 1 to 2 x10E7Amps/sq-cm by 6 or 10. At the extremes does that not give a result of 6 x 10E7 and 2x 10E8Amps/sq-cm?
You are now claiming that I need to understand the geometry and nature of the cell. I think I do. So what next do you think I need to understand.
My view is what you need to understand the effect of current densities of 1x 10E7Amps/sq-cm to 1x 10E8Amps/sq-cm,, especially in relation to electro-migration. Your position appears to be that current densities of that level are safe and will give rise to reliable PCM product. Mine is I am prepared to make that statement when I fully understand the effects and consequences. Until that time I would suggest caution and you perhaps ascribing a question mark on PCM reliability and scaling.
(As an aside I am reluctant to take advice from somebody hiding behind a user name I am prepared to make clear who I am, why do you find that difficult in an honest debate or discussion?)
As a correction - I never suggested that Numonyx had a range of current density from “6 x 10E7Amps/sq-cm to 2 x10E8Amps/sq-cm”. I stated that the range of current you gave was low by a factor of 6-10 and gave the reference to a figure and paper that showed an operating current density of 1.3 X10E8 Amps/sq-cm for the 45 nm node . I should have more precisely stated that the current density range you were giving was low by a factor of 6.5 - 13.
In regards to calculating current density - it is not a question on being on the generous side or erring on the safe side “for fairness” – it is a matter of understanding the geometry of and structure of the PCM cell and utilizing a correct methodology to calculate the actual current density. In the all the recent PCM cell structures by Samsung, Hynix, Numonyx and IBM/Macronix a form of sub-lithographic technique (or ebeam in the case of the IBM line cell) is utilized to reduce the PCM storage area. The proposed sub-litho methods vary drastically and for a given cell technology and one can debate the manufacturability / scalability and controllability of the individual technique. However, it is erroneous to ignore the underlying device structure and associated sub litho technique incorporated in the cell construction in any meaningful current density calculation used to compare different cell technologies and geometries
While the concept of "phase change in some materials such as colcogenide materials" leading to "distinct resistive states",
was brilliant (several decades ago) it could not in any ways compete with current flash. Those who preached for PCM,
wanted to displace current Flash they do not master well the art (current flash technology that is). Current Flash continued to scale until today. Current Flash allows precise charge trapping in floating gate.
This precise control of charge led to Multiple Bits per cell. PCM would have hard time accomodating Multiple Bits per cell as excessive temperature (600C for programming) and material consistency (due to electromigration and other) "may" get in the way.
Therefore, I do not believe one can adjust the cell resistance that easy considering the melten material. In addition, considering chip thermal capacitance and poor thermal conductivity of materials such as oxide in isolation or oxide/nitride used for
passivations, or package, cell temperature will not drop that easy as claimed in the past (few nanoseconds)! Perhaps true in the open air.
In the package, some sort of heat dissipators may be needed to prevent "thermal build-up" that can raise junction temperature leading to inacceptable leakage that may push the silicon toward intrinsec regime. Furthermore, one has to have distinct programmed / erased windows. The resistance associated with these windows must be relatively high so it is not easily affected by parasitic resistances (contact, interconnect, etc.). Therefore, one must rely on, relatively speaking, power devices (high current coupled with high voltage) to enable adequat programming.
Finally, from what I see all along, I consider the PCM a laboratory curiosity and it is outdated. It could have had a place in history several decades ago, but short lived! Doing R&D on thing like PCM is fine, but for several decades at the expense of investors is wrong!
Some additional thoughts:
Coming with one or several reliable disruptive approaches for memories do not hurt as the technologies currently used in Flash ,
for storage or execute in place, and DRAM are reaching road blocks. Having watched the PCM for a long time, and I happend to have worked for Intel
where I could not understand the need for PCM while NAND and NOR still have plenty of room for scalability.
I do not believe that one can claim victory or making claims as reported the last decade or so, mainly by Intel/Numonyx.
With all the claims one would think there must be "some volume manufacturing of PCM"!
CORRECTION To convey the intended sense please replace "Low" with "High" in the following paragraph.
Low number laboratory demonstrations of PCM w/e life times, have been difficult to turn into reliable PCM array products.
ExDRAMer- I based my calculation for the Numonyx current density on the published reset current and used the lithographic node 45nm. In my paper, I have acknowledged that if sub-lithographic techniques are used then the (J) values will be higher. I may have been generous in my estimate but I think in all fairness it is better I erred on the safe side. I did have some concern that from my calculation that Numonyx appeared to have been able to buck the historical trend of all PCM reset current density data that I have been collecting.
The range of numbers for (J) you have suggested for Numonyx, 6 x 10E7Amps/sq-cm to 2 x10E8Amps/sq-cm would put the device in what I chose to characterize as the reliability danger zone. It also might explain why the much heralded, 1 G-bit PCM product is not readily available in the market place, or has been relegated to demonstration vehicle status.
Historically, it has always been possible to demonstrate high number write/erase lifetimes. When the Electronics 1970 paper was published PCM devices had W/E lifetimes of 10E6 write/erase cycles, with some under special conditions even higher. However, if you examine the data sheets of the time, they specify 600W/E cycles and suggest recovery by the use of multiple reset pulses. Low number laboratory demonstrations of PCM w/e life times, have been difficult to turn into reliable PCM array products.
With respect to your comment “molten phase change volume”, in my paper, I have also discussed, the benefits of moving the active region away from the electrodes. I have characterized this as “Thermal Engineering” and how it accounts for PCM reported current densities that appear to go against the historical trend with reductions in fabrication lithography. It has both pros and cons, it may also be used to account for the apparent increase in w/e lifetime.
ex-DRAMer mentioned: "As the PCM cell type migrates with scaling to a confined (constrained) cell the high temperature molten phase change volume is moved away from the electrodes minimizing the temperature at the electrode phase change layer interface leading to significantly enhanced cycle endurance of greater 1x10E10 to 1x10E11 " We have tried this and found the confining approach definitely reduces the RESET current and theoretically reduces SET time. However, due to the longer strip of higher resistance of the confining section, the operation voltage increases. It was the opposite trend of the expectation of DRAM makers and foundries. For Flash makers, it was okay. But the power consumption for PCM is larger than for flash. So we could not make the larger number of cycles appear attractive. The last feature we tried to grab was MLC, but this is defeated even with limited temperature range when you consider the resistance drift.
I don’t have a crystal ball and never intended to estimate when PCM will be “billions of dollars of sales”. My main point was that PCM does not need wait until 1x or 2x production to enter the market place. It is a simple statement of fact that the NOR market has not disappeared and is still today a multi-billon dollar market. I believe a realsitic estimate for PCM market valuation was given by a Samsung interview in The Korea Herald:
“Memory for portable consumer devices today is at a major turning point as mobile applications increasingly require more diverse memory technology,” said Jun Dong-soo, an executive vice president at Samsung Electronics.
“The launch of our PRAM in an advanced MCP solution for the replacement of 40 nm-class and finer geometry NOR meets this need head-on,” he said.
Samsung plans to increase the lineup of its large-capacity, high-performance PRAM products and expand PRAM applications to other mobile devices such as MP3 players, portable multimedia players and navigational devices, as well as solid state drives and HDTVs.
Samsung expected the global PRAM market to reach $10 million this year and grow to $120 million in 2011, $350 million in 2012 “  The sales of PCM in this timeframe will be on technology greater than 1x-2X nodes. Note the initial PRAM application in MP3 players and solid state drives is not to displace NAND, but rather to act a low latency buffer in the SSD / MP3 memory hierarchy enhancing the system level performance.
 “Samsung supplies first PRAM for handsets” The Korea Herald 2010-04-28 http://www.koreaherald.com/national/Detail.jsp?newsMLId=20100428000630
Prior to publishing your article I suggest that you revisit your methodology for calculating current density because your ‘suggested’ “1to2x10E7Amps/sq-cm” for Numonyx 1 Gb 45 nm is low by a factor of 6-10 based on Numonyx’s published current density for their 45 nm technology. See figure 12 from previous cited reference where the device endurance is reported as a function of programming current density for their 180, 90 and 45 nm PCM technology nodes . In the previously cited reference by Samsung the cycle endurance was reported at 1x10E11 cycles for the reported 6.3 X10E7 A/sq-cm .
In both the cited Numonyx and Samsung PCM technologies the PCM active region of the storage element is realized by the intersection of a lithographic feature with a deposited thin film heater that can be in the range of 10 times smaller than the lithographic capability [1.3,5]
It was never claimed that Chalcogenide nor the electrodes utilized in PCM cells are rare materials free from the effects of electromigration. There have been numerous articles published on failure analysis of cycle life failures in PCM and they show electromigration / compositional changes are indeed the dominant failure mode, but the failures occur at cycle endurance values well past current flash cycle endurance values. As stated and cited previously “no impact is observed (for cycling endurance) on scaled devices where the higher current density values are needed to reach the same GST melting temperature” .
As the PCM cell type migrates with scaling to a confined (constrained) cell the high temperature molten phase change volume is moved away from the electrodes minimizing the temperature at the electrode phase change layer interface leading to significantly enhanced cycle endurance of greater 1x10E10 to 1x10E11 [1,5].
 D.H. Im et al.,” A Unified 7.5nm Dash-Type Confined Cell for High Performance PRAM Device” IEDM Tech. Dig., p. 211 , 2008
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