If the views of Greg Atwood of Micron Technology on phase-change memory (PCM) scalability are a measure of the quality of his paper, The evolution of phase-change memory, then its overall value is suspect.
Atwood writes: “Scalability is one of the major motivations for the development of PCM”. He relies on facts with respect to scalability that may have been true in the early history of PCM development, but no longer match the situation.
His argument that the scaling of the number of electrons stored in a flash memory can be compared to a material that can change its phase is naive.
A more realistic comparison would be with the means by which the phase change is achieved and the consequences that come with scaling. The power required to heat the PCM material to 600 degrees C (cherry red) requires current and the reset current scales with minimum lithographic dimensions. This is true at larger lithographic nodes when the initiating molten hotspot of the PCM is relatively well distanced from the surrounding electrodes and dielectric.
Current scaling continues with shrinking dimensions but current density (J) does not. The reason is the volume of material in which heat can be generated is decreasing as r3 while the cooling area is decreasing as r2. The spherical case is a good approximation.
From the literature and from consideration of published results, current densities of up to 2x10E8 A/sq-cm would be expected for devices with dimensions of from 5- to 20-nm.
Does Atwood suggest, as he makes his case for scaling, that current densities at the levels cited above, flowing in molten chalcogenide have no effect? Electro-migration must occur and change the composition in the direction of current flow. What, with scaling, will be the impact of that change on write/erase lifetime, elevated temperature data storage and other device parameters and reliability?
My examination of the published results, (including Samsung ), indicates that by increasing the length-to-diameter aspect ratio of constrained PCM structures, i.e thermal engineering, it is possible to make what appears to be some promising progress toward lower current densities with reducing lithographic dimensions. The result is PCM current densities of 1 to 3 x10E7 A/sq-cm for devices in the 40-nm range. However, this approach most likely incurs a process yield problem, and self-evident thermal considerations limit the value of this approach before the current density starts to increase again. The thermal benefit of making devices longer by moving the electrodes away from the active volume is limited.
The next PCM scalability problem that Atwood ignores is the effect of current density on the matrix isolation device. Tightly packed bipolar or MOS devices do not operate reliably at the current densities that will be required at PCM dimensions in the range 5 to 30 nm. Perhaps his claims for PCM scalability would appear to rest on the development of a new type of matrix isolation device. (For this, IBM has suggested in a recent paper  that the way forward would be an if-you-cannot-beat-them-join-them approach to electro-migration and use of ionic copper conduction in a matrix isolation threshold switch they have developed for 3-D PCM). Is this what Atwood meant by solid state disk drives?
I am tempted to suggest that in a highly constrained PCM cell it might be possible to create a situation where the electro-migration flux exactly balances the thermal back-diffusion flux. For the moment I will leave that to others.
In light of the above and your claims for scalability, what does “ready for prime time as a next-generation nonvolatile memory” actually mean? A more detailed explanation from Micron, your new employer, would be helpful with a product roadmap and time lines.
My view is there still is a lot more work to be done.
R. G. Neale
Former editor-in-chief of Electronic Engineering
Co-author of Nonvolatile and reprogrammable, the read-mostly memory is here, by R.G.Neale, D.L.Nelson and Gordon E. Moore, Electronics, pp56-60, Sept. 28, 1970.
 Highly scalable on-axis confined cell structure for high density PRAM beyond 256Mb, S.L.Cho et al., Samsung, Symposium on VLSI Technology, 2005
 Highly-scalable novel access device based on mixed ionic electronic conduction (MIEC) materials for high density phase change memory (PCM) arrays, K. Gopalakrishnan et al., IBM Almaden Research Center, USA, Symposium on VLSI Technology, 2010.