Electron beam (e-beam) lithography is becoming increasingly more critical to semiconductor manufacturing. Not only is e-beam lithography essential for the future of direct-write applications for wafers, but also for all precision photomasks that will continue to be written by e-beam. In addition, extreme ultraviolet (EUV) lithography masks as well as nano-imprint masks will also be written by e-beam. In other words, no matter which lithography approach is used to write wafers, all leading-edge designs will require e-beam technology. Yet, the amount of investment in e-beam technologies around the globe is lacking as compared to those in other semiconductor technologies. However, a recent development in design-for-e-beam (DFEB) mask technology demonstrates how an investment across the supply chain in e-beam technology can significantly increase options for the economical production of semiconductors at future geometries.
E-beam lithography represents a trade-off of accuracy and write times. E-beam is inherently more accurate and precise at writing nanometer-level features as compared to light. In addition, 50KV e-beams are excellent at depth of focus, making them a superior choice for drilling holes. However, when writing wafers, e-beam-based direct-write takes much longer than mask-based writing using light. On the other hand, for e-beam-based mask writing, the trade-off is between the quality of the wafers produced and the write times of the masks needed to produce those wafers.
At 22-nm logic nodes (32-nm half pitch), the wafer manufacturing for system-on-chips (SOCs) will need to rely on 193-nm immersion lithography. EUV lithography will not be economically or operationally practical for all but the highest volume designs. E-beam direct-write and nano-imprint technologies provide maskless alternatives for low-volume production, but are not fast enough for mass production.
The problem with 22-nm volume production printing with 193-nm immersion is that the features are so small that complex shapes will be required on the mask in order to produce adequate wafer yield. These complex shapes cause the mask write times to explode, making the mask costs unacceptable. Going the other way, the mask shop’s concern for the mask write times forces a constraint on the incoming mask shapes to be less complex. This constraint forces the optical proximity correction (OPC), inverse lithography technology, computational lithography, and/or source mask optimization solutions to be limited to "Manhattanized" solutions where the shapes consist of horizontal or vertical rectangles only. The basic engineering assumption to use only non-overlapping rectangles built into today’s CAD and lithographic systems is at the heart of the problem.
For 32nm-half pitch and below, the ability to use circles for mask lithography becomes critical, both for design and for manufacturing. The key to using circles lies in the CAD system that fractures design data into mask shapes. The exclusive use of non-overlapping rectangles to create all shapes on a mask simplifies the fracturing process, but creates possibly insurmountable throughput issues at advanced nodes. New DFEB mask technology enables fracturing into circles as well as rectangles and allows overlapping shapes to create curvilinear features with far fewer e-beam shots which results in faster write times. The collaboration and investment of the e-beam ecosystem enables circles to be used in lithography for today’s most advanced nodes, and extends the useful life of optical lithography for another generation of masks.
Currently, there are European, U.S., and Japanese government programs investing in e-beam technologies, and while both vendor and customer investments continue as illustrated by the DFEB mask technology, the amount of total funding available is not reflecting the amount of promise these technologies represent in enabling cheaper and earlier design starts for future technology nodes. These investments are still short of what is required to bring production capabilities to market on time for the impending sub-30-nm technology node. Further advances are required in key e-beam technology areas, such as e-beam writing equipment for both photomasks and wafers, resist technology development, simulation software development, and inspection equipment development. With more investment from both the public and the private sectors from across the globe, character projection, multiple-column cell (MCC), multi-beam, and hybrid technologies like multiple-shaped beam (MSB) technologies will become realities sooner for both mask making and wafer manufacturing. E-beam technology can significantly enhance wafer yield ramp of new nodes, decrease the cost of manufacturing and enable more design starts earlier for advanced nodes.
Aki Fujimura is CEO of D2S Inc., which provides a computational design platform to maximize existing e-beam technology to reduce
This is a really nice piece, thanks very much. Perhaps some comments, more general in nature, are in order.
First, going down below 40 nm, no matter what radiation you use, the resist is going to limit you, either in throughput or resolution. Particularly these chemically amplified types.
Second, at the same dose, smaller features use less incident particles (photons, electrons, etc.) so are naturally more prone to random dose variations (sometimes called shot noise).
Third, the CD vs dose model needs to be discussed much more openly especially as more critical features are being added.
Join our online Radio Show on Friday 11th July starting at 2:00pm Eastern, when EETimes editor of all things fun and interesting, Max Maxfield, and embedded systems expert, Jack Ganssle, will debate as to just what is, and is not, and embedded system.