The semiconductor industry may stay on track with Moore's Law even if it delays scaling down, while finding a better solution for interconnect and lithography by scaling up-to the third dimension.
I was intrigued by Marvell CEO Sehat Sutardja's call in EE Times to "change and rethink Moore's Law to include the long-ignored fourth dimension" of power consumption efficiency. "What we need now is a new social contract," Sutardja wrote.
Calling Moore's Law a social contract is one way to look at it. Others see it as a self-fulfilling prophecy, or at least it has been so for the past 45 years. Ray Kurzweil claims it is a part of the Law of Accelerating Returns, whereby computing devices have been consistently multiplying their computational power at least since 1890 and possibly for centuries before that. I take Kurzweil's optimistic view; my rationale is that better computing power created in one generation enables us to develop a better computer with the next generation, thereby creating a positive feedback loop for an exponential growth of computing and related domains.
In the famous 1975 IEDM paper that begat Moore's Law, Gordon Moore predicted the annual doubling of chip complexity as a result of three trends, only one of which was scaling. Despite that, over the past two decades Moore's Law manifested itself mainly as a 0.7 scaling for every process node, yielding the full factor-of-two density improvement on its own.
The early days of scaling were the most rewarding. As Moore stated: "By making things smaller, everything gets better simultaneously. There is little need for trade-offs. The speed of our products goes up, the power consumption goes down, system reliability, as we put more of the system on a chip, improves by leaps and bounds, but especially the cost of doing things electronically drops as a result of the technology" (Moore, SPIE 1995). Those were the good old days. There was no need to call for a new social contract; power efficiency came naturally with scaling, as smaller transistors had smaller gate capacity and burned less dynamic power. And further efficiencies were achieved by lowering the operating voltage all the way from 5 volts to less than a volt.
But going forward with just scaling does not look as bright. Further reduction of operating voltage will cause severe reductions in performance, and further reductions in gate capacitance will have only a negligible impact on dynamic power (interconnect capacitance these days far exceeds the gate capacitance). While lithography scaling provides all the benefits with respect to the transistors, it provides none with respect to interconnect; in fact, it just gets worse. The industry had moved from two metal layers all the way to 10 metal layers, then from aluminum to copper, and recently from the convenience of SiO2 to the challenging low-k dielectric, with some even predicting air in the future. Yet the tyranny of interconnects requires us to consider other alternatives.