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A wakeup call for the global semiconductor supply chain

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4/19/2011 04:57 AM EDT

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daleste
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re: A wakeup call for the global semiconductor supply chain
daleste   4/28/2011 4:38:47 AM
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Having a back up for standard off the shelf ICs is pretty easy. The problem occurs when the IC needed is a custom design. It could be an ASIC or a full custom chip. Large companies that have multiple fabs may be able to offer a second source in another fab. This is often an acceptable solution. I just don't see as many customers requiring a second source as they used to.

yehudaby@kaisemi.com
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re: A wakeup call for the global semiconductor supply chain
yehudaby@kaisemi.com   4/21/2011 5:23:57 PM
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Dear Jhchang, No one said or think that "These get done in a day", especially someone like me which is in the silicon business for so many years. I know and understand the issues, the costs, the time, the "pain" but still it is doable, exactly as the first one was. It is not easy, but I still think that "Building backup and alternative manufacturing solutions can begin in parallel, in overlap or following the main tapeout with some affordable trade offs. Whenever high quantities are involved, these additional NRE costs should be economically justified." Thank you, Yehuda

yehudaby@kaisemi.com
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re: A wakeup call for the global semiconductor supply chain
yehudaby@kaisemi.com   4/21/2011 5:12:11 PM
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Dear Gabriel, I think you should read my post more carefully as I have never said or mentioned another offering of FPGA as a solution. Kaisemi does not offer FPGAs. I was talking only on ASICs and special ICs, which are ordered by demand and not available regularly on the shelve. Please see our site. It is completely clear to everyone in this business that this solution is not simple but doable. It is suitable to many required ASICs and probably irrelevant to many others, for many reasons. The main thing I wanted to say is that specific ASICs (and not only them) which are critical to the supply chain should be available in one of the ways (inventory, parallel FABs, etc.) for a certain recovery time when a serious disruption appears. Today everyone try to minimize or avoid inventory. Fast Asic-to-Asic conversion is one of the ways for a fast recovery, if nothing else is available, even so not suitable to all ICs. Thank you, Yehuda

jhchang
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re: A wakeup call for the global semiconductor supply chain
jhchang   4/19/2011 5:11:23 PM
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Ben-Yaish, having design resources in multiple places is hardly the beginning of having a functioning, error-free semiconductor device. With design rules hitting 30nm or below these days, proper process set of and qualification of each location are critical. These do not get done in a day, you know? Too many electrical/design engineers in the semiconductor industry think error-free processes come for free and painless.

Eyenot
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re: A wakeup call for the global semiconductor supply chain
Eyenot   4/19/2011 12:10:27 PM
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Ben-Yaish, You argue that the answer is to continue the fabless model (as lucrative as it's been to a few) with a new backup chain offering FPGAs. I doubt there will simply be a humongous surge in demand analogous to the loss in supply created by the Japanese earthquake. While the redundancy in the design of FPGA allows "fast and seamless conversion," (though with obvious and striking differences between the performance of FPGA and hard ICs) "into identical components," high initial cost to logistic redundancy times high initial cost to design redundancy equals a rather expensive "secondary but vital" existence, like some Shaharazadian vizier's dream. Pre-news: [ http://www.technologyreview.com/computing/37406/?p1=A1&a=f ] I paraphrase: "The new chips are a cheaper, more powerful competitor. Says Steve Teig, founder and chief technology officer of Tabula, his company's reprogrammable design is considerably smaller than that of an FPGA. 'From its behavior, our [design] is indistinguishable from a stack of chips,' says Teig, making it 5*cheaper to make, providing more than 2*density of logic and roughly 4*performance." [Basically, built-in paging]. Even if you proposed Teig's FPGA instead of your own, there would still be a flawed logistic. If the problem was, at first, that far-off supply was inherently unstable, why build a second chain equally as long and not even always needed? The fabless, JIT model is showing it's greatest failure right now: the chips aren't here. I understand why anyone would seriously suggest manufacturing more redundancy to be more synchronized, but only if they obviously would stand to profit. What you should promote is getting out of the fabless model entirely. Obviously, with Texas Instruments acquiring National Semiconductor, there should be no more doubt (at least in America) that "real men have fabs". -- Gabriel Arthur Petrie Student of electronics and manufacturing

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