Applied Materials' announcement of a new application for its Reflexion GT CMP system opens a window on the pitched battle that process and equipment engineers are fighting against process variations as the industry lumbers toward the 20-nm node.
Applied Materials' announcement this week of a new application for its Reflexion GT chemical-mechanical polishing (CMP) system may seem an arcane detail to engineers outside the process-integration community. But the event opens a window on the pitched battle that process and equipment engineers are fighting against process variations as the industry lumbers toward the 20-nm node.
Applied's Reflexion GT is widely used at advanced nodes for planarizing the copper-damascene interconnect layers-basically, grinding them flat so that the next layer will start on a flat surface. The company today announced a new application: planarization of the contact layer-the insulating layer through which tungsten plugs connect the interconnect layers to the transistors -- at geometries below 32 nm in logic processes. The tool will also be used in advanced flash and buried-line DRAM processes, but we will focus here on logic.
In these processes, you form the contact layer in several steps. You etch through the oxide layer, which lies directly on top of the transistors, to open tiny holes down to the source and drain surfaces of the transistors. FinFET structures add a bit of complexity here, because the finFET stands on top of the silicon instead of lying in it. In the case of finFETs, you are actually opening tiny rectangular trenches that intersect the gate electrodes on either side of the transistor's fin.
In either case, once you have opened the hole, you deposit a barrier material at the bottom of the hole, and then carefully clean the material off of the rest of the wafer. Then you cover the whole surface of the wafer with metallic tungsten, filling in all the holes and leaving a sheet of the metal covering the wafer. Now comes the CMP part. You use the CMP system to polish away the tungsten down to the surface of the oxide, leaving only the tungsten plugs in the contact holes.
The trick here is uniformity. Applied global product manager Sidney Huey said that by the 20-nm logic node, foundries will need under-25-nm flatness across the whole yielding surface of their 300-mm wafers. To achieve this, the Reflexion GT induces and measures eddy currents in the tungsten sheet to estimate the remaining thickness of the metal layer, and uses this thickness information as an error signal in a closed-loop control system to adjust the pressures on five independent regions of the polishing platen.
The main reason flatness is so important at the contact layer is electrical. As the polish removes the last of the tungsten from the surface of the oxide, there will be high spots where tungsten remains on the wafer, and low spots where oxide-and the tops of the contact plugs-are exposed. In the final seconds as the last surface metal disappears, the polish will eat into the tops of the exposed contact plugs, making them concave.
But these plugs are so shallow-sometimes on the order of 100 nm-that a little concavity can mean a significant difference in the effective length of the contact, and hence in the contact resistance. This is especially true on the long, narrow, and shallow rectangular contacts on those finFETs.
Thus small changes in surface planarity during CMP result in significant on-chip and chip-to-chip variations in contact resistance. But contact resistance is a critical parameter in the transistor models, with a strong impact on cell-level timing. So Applied's ability to control surface roughness on the contact layer will influence the mean and distribution of delays at the circuit level. This, in turn, will influence timing closure. More subtly, the distribution of contact resistance variation, and its randomness or spatial correlation, will in the end influence whether design teams can continue to get away with traditional static timing tools, or whether they will have to move to fully statistical tools for sign-off, or even earlier, during timing closure.
As we move deeper into impossible geometries, strong but implausible links are forming across the design chain, from semiconductor equipment designers' choices through the chip design flow and into manufacturing. The chain is becoming a web.
This story was originally posted by EDN.