A false belief that leading-edge chips cost up to $100 million to develop has severely decimated levels of venture capital investment in semiconductors, diminishing innovation in our industry and our economy. The fact is, engineers can create a profitable chip company with less than $2 million of total investment. I know because we have done it.
An exponential increase in mask costs is cited most often as the reason chips have become so expensive. Mask costs have risen from $100,000 to as much as $1-$3 million, but this factor alone cannot explain why some chips costs $100 million to develop.
Some blame the high costs of EDA tools. While they are certainly not cheap, on a per-project basis EDA tool costs have actually decreased significantly. Today many leading-chips can be taped out using vanilla flows derived from reference scripts provided by the EDA vendor. Thus, per transistor and certainly per project, the cost of EDA tools has actually gone down in the last ten years.
Others say deep submicron design is getting really hard. This work definitely is not for hobbyists, but for a small expert team equipped with state-of-the-art tools, it is today possible to accomplish in weeks what used to take a generously sized team 6-9 months.
The most valid reason for the recent explosion in development costs is that chips are getting really complex. Indeed, design complexity is by far the biggest component in a SoC project’s costs, and it varies widely depending on the type of chip. A complex SoC can be a hundred times more complicated than a high performance ASIC. And, as experienced project managers know, complexity is always expensive whether it involves SoCs, FPGAs or software products.
Based on my personal experience, observations and conversations with chip startup executives who spent, on average, $50 million on SoC development, engineering salaries are by far the biggest cost in SOC design. (See figure below.)
costs for a complex SoC product (Total: ~$50M)
What market you choose is the most important decision determining the cost of chip development. Markets that are not quite as cost- and space-sensitive as consumer devices have a huge advantage in development cost savings, because they allow companies to leverage existing technology to make chip set solutions that satisfy the system requirements. At Adapteva, we chose military, embedded computing and high performance computing as initial markets because of readiness of the market and the capability to customize for these markets.
Here are a few other simple ways to reduce chip product development expenses:
- Reduce the feature set that needs to be implemented.
- Maximize the reuse of validated blocks and RTL code.
- Leverage off-the-shelf technology.
- Recycle all the great chip ideas of the last 70 years
- Design architectures that leverage existing open-source software.
- Make processors programmable in C.
- Make the chip attractive and easy enough to use, so that the user won’t mind programming it himself.
Designing architectures that can easily be verified with a small team is an art form that requires very tight integration between the architecture, design and verification teams. At Adapteva, we staffed-up extremely slowly and took our time to perfect the mask cost until absolutely ready. The unity of the design team was critical to our success.
Focusing on the company’s core competency is critical in order to keep costs under control. We were lucky to find great tier-one development partners for manufacturing, development tools, board development and marketing.
At Adapteva, we used many of these techniques to reduce each cost item by more than 90 percent. We have now reached product release and a company break–even point with less than $2 million of total investment. Along the way, we completed four generations of our Epiphany multicore products.--Andreas Olofsson is chief executive of Adapteva (Lexington, Mass.).