SAN JOSE, Calif. – For all the news today around Intel’s E5-2600 announcement, there’s still a handful of untold stories behind this latest server processor. The big one to me is what the chip and products around it say about the looming I/O bottleneck.
An Intel manager confirmed what analyst Linley Gwennap first told me: The Intel Romley server motherboards based on the new chip were delayed due to difficulties verifying the PCI Express Gen 3 interconnects they used.
At 8 GTransfers/second max, PCIe Gen 3 is a screaming link for a PC. Intel had never previously designed a board or chip with the technology. I suspect the CPU itself was delayed—though Intel officially says it was not—because it too was Intel’s first design to integrate the fast interconnect.
Interestingly, the PCI Special Interest Group (SIG) actually backed off the gas a bit with PCIe 3. Rather than double the 5 GT/s maximum data rate of Gen 2 it opted for an easier target of 8 not 10 GT/s so as not to stress the cost-constrained PC supply chain. However, the SIG also specified a move from 8b/10b to 128b/130b encoding so that total maximum bit rate would still be doubled with Gen 3.
You can bet if Intel felt some growing pains with this design, a lot of less technically sophisticated companies in the x86 ecosystem will be burning the midnight oil over the next year or two.
It’s only going to get harder. With PCIe Gen 4, the SIG went for the gusto, doubling the data rate to 16 GT/s. However, some had pushed to choose 24 GT/s, a speed that got tested in the labs but rejected as too aggressive.
Backers of the faster data rate argued that Gen 4 might well be the last version of PCIe over copper. So why not squeeze every drop of data you can get from it, they asked.
The assumption is PCIe some five to eight years from now will either need a ground up redesign for optical channels or require some breakthrough in fast but low cost copper signaling. A few smart engineers may earn PhDs on this one.
The I/O crunch will put pressure on chip designers to pack more into the chip—or the package. Indeed by the time PCI Gen 4 makes its way into systems in about 2016, 3-D IC stacks with through silicon vias should start emerging in several sectors, starting with mobile applications processors.
A nice 3-D IC stack could help fend off a need to go to optical PC boards or find a copper breakthrough in 2020. But 3-D ICs require some heavy lifting of their own—there’s no free lunch.
This is a familiar story to embedded systems folks. CPU speeds have been growing much more quickly than interconnect speeds, be they for local memory, storage, or remote databases. At some point I think we will need to reexamine the system architecture of a computer itself to decentralize the compute elements across the data instead of building ever-faster roads for the data to get to the CPU.
David Patterson, known for his pioneering research that led to RAID, clusters and more, is part of a team at UC Berkeley that recently made its RISC-V processor architecture an open source hardware offering. We talk with Patterson and one of his colleagues behind the effort about the opportunities they see, what new kinds of designs they hope to enable and what it means for today’s commercial processor giants such as Intel, ARM and Imagination Technologies.