SAN FRANCISCO – It’s the beginning of the end for the fabless model according to Mark Bohr, the man I think of as Mr. Process Technology at Intel.
Bohr claims TSMC’s recent announcement it will serve just one flavor of 20 nm process technology is an admission of failure. The Taiwan fab giant apparently cannot make at its next major node the kind of 3-D transistors needed mitigate leakage current, Bohr said.
“Qualcomm won’t be able to use that [20 nm] process,” Bohr told me in an impromptu discussion at yesterday’s press event where Intel announced its Ivy Bridge CPUs made in its tri-gate 22 nm process. “The foundry model is collapsing,” he told me.
Of course Intel would like the world to believe that only it can create the complex semiconductor technology the world needs. Not TSMC that serves competitors like Qualcomm or GlobalFoundries that makes chips for Intel’s archrival AMD.
Intel used the Ivy Bridge event to spin the tale of how part of the secret to its success is its close partnership between process and chip designers.
Kirk Skaugen, the new general manager of Intel’s client PC group, moderated a Q&A with Bohr and Brad Heaney, the Ivy Bridge program manager. In addition to working together on Intel’s first CPUs using 3-D transistors, the two collaborated on Intel’s first processors using high-K metal gate technology.
“Being an integrated device manufacturer really helps us solve the problems dealing with devices this small and complex,” Bohr said in the Q&A.
I don’t doubt that for a minute. Since the dawn of submicron design, EE Times has been writing about the need for ever closer collaboration between chip and process designers. An Nvidia physical design exec underlined the same point in a recent talk at Mentor Graphics’ annual user group meeting.
But Bohr stretches the point too far when he says the foundries and fabless companies won’t be able to follow where Intel is going. I have heard top TSMC and GlobalFoundries R&D managers make a good case that 3-D transistors won’t be needed until the 14 nm generation. For its part, TSMC said at 20 nm there is not enough wiggle room to create significant variations for high performance versus low power processes.
I neglected to ask Bohr whether Intel has separate high performance and low power processes in its 22 nm technology. (Anyone from Intel is welcome to chime in here.)
However, in an open Q&A, Bohr said Intel has completed work on an SoC-specific version of its process technology. It plans going forward to have an SoC variant a quarter or two after each main process is complete.
For its part, Qualcomm would not provide its opinions on TSMC’s 20 nm plans. The company did say in its recent quarterly earnings call it can’t get enough 28 nm technology from TSMC to meet product demand, so it is working to develop multiple new sources it expects will come online later this year.
That’s a big opportunity for a GlobalFoundries, UMC or other fabs to step up. Given the close sharing of design details required to make 28 nm SoCs, it’s more of a risk than an opportunity for Qualcomm to work with Samsung’s foundry folks, Bohr said, given Samsung has its own Exynos mobile SoCs.
I asked Bohr to whom Intel is providing access to its 22 nm process besides two announced partners—Achronix and Netronome. He only said that Intel does not want to be in the general foundry business, but it makes its technology available to a few strategic partners.
Intel has no monopoly on smart process technology engineers and designers. But it does have some brilliant ones, and it has learned to market them smartly. Bohr and Heaney even appeared yesterday in another one of Intel’s playful videos shrinking the two engineers so they could tour the insides of an Ivy Bridge chip.
Looking ahead, Bohr said Intel has finished characterizing its next-generation 14 nm process using immersion lithography. It even has “encouraging results” suggesting it will be able to use immersion litho for the 10 nm node that is still in early planning phase.
“We think we have a [10nm] solution using immersion lithography—we’d love to have extreme ultraviolet [EUV] lithography, but we are not counting on it,” said Bohr in the event Q&A.
As a follow up, I asked whether Intel has other new process tricks like 3-D transistors at 14 and 10 nm. His answer: “Yes!”
I love it when companies celebrate and provide access to their top engineers. But I hate it when they are so well trained by their PR departments.
Skaugen (left) queries Bohr and Heaney (right) on their process/chip design collaboration.
If you take a fat unfit person (like me) and tie the latest carbon fibre running shoes on my feet it won't help. An athlete with boots on will still run faster.
The same goes for CPUs.
Intel might be ahead in process, but that does not give them a lead overall because their architecture is so terrible.
ARM stuff is still better for most applications even when built on older (and thus cheaper) fab technologies.
At the launch of Ivy Bridge ( 22 nm finFET ) last week the offical Intel claim was 20 % higher performance for 20 % lower power. Would that be good enough to scare established Fabless providers of SoCs for Mobiles to abandon their generic ARM based design / Foundry / high mark - up model and switch to X86 ? Is Intel prepared to also offer some price cuts to get a design win into SmartPhone / Tablets?
Let's not be naive: of course Intel won't praise the fabless model!
Everybody claim to have the best approach, and it's no surprise that other foundries claim 3D is not required before 14nm (going further: "you see? Intel is wasting so much money just to show off and try to justify their IDM approach!")
I'll be convinced about all of that when I'll see Intel's procs outperforming all their competitors.
Beside, if I was Intel, I'd be more careful about these claims, because we don't know how long they'll be able to compete alone in the Moore's law race...
Very interesting, but over the years the number of times we see one company thinking they have a large headstart over others is legion and even more so the number of times they find that the others can come up with other ways to do the same thing. One of the most interesting was something many may remember called "micro-channel" back in the 90's. Everybody else just came up with another way to accomplish the same thing. I suspect we'll see the same here.
It would seems that Mark statement should be taken far more seriously !Lets recall the recent NVIDIA bashing of TSMC - see my recent blog: "Is NVIDIA in a Panic? If so, what about AMD? Other fabless companies?"
Clearly Intel have significant advantage these days by being able to control the design, the EDA and Libraries and the fab.For the fabless module to work the largest fabless companies need to establish partnership with the EDA/Libraries provider and the foundry.But this will be very hard to do.
Alternatively they can change the game (to monolithic 3D IC ;-)
The fabless model will continue to function but not at the leading edge. As EUV/X-ray continues to be endlessly strung out, stretching optical will require ever more magical DFM (remember DFM?) tricks and spaceless links between design and manufacturing. The foundries will cling to their guns, bibles and recipes, while fabless designers will be forced to innovate with sub-leading edge processes.
David Patterson, known for his pioneering research that led to RAID, clusters and more, is part of a team at UC Berkeley that recently made its RISC-V processor architecture an open source hardware offering. We talk with Patterson and one of his colleagues behind the effort about the opportunities they see, what new kinds of designs they hope to enable and what it means for today’s commercial processor giants such as Intel, ARM and Imagination Technologies.