SAN FRANCISCO – It’s the beginning of the end for the fabless model according to Mark Bohr, the man I think of as Mr. Process Technology at Intel.
Bohr claims TSMC’s recent announcement it will serve just one flavor of 20 nm process technology is an admission of failure. The Taiwan fab giant apparently cannot make at its next major node the kind of 3-D transistors needed mitigate leakage current, Bohr said.
“Qualcomm won’t be able to use that [20 nm] process,” Bohr told me in an impromptu discussion at yesterday’s press event where Intel announced its Ivy Bridge CPUs made in its tri-gate 22 nm process. “The foundry model is collapsing,” he told me.
Of course Intel would like the world to believe that only it can create the complex semiconductor technology the world needs. Not TSMC that serves competitors like Qualcomm or GlobalFoundries that makes chips for Intel’s archrival AMD.
Intel used the Ivy Bridge event to spin the tale of how part of the secret to its success is its close partnership between process and chip designers.
Kirk Skaugen, the new general manager of Intel’s client PC group, moderated a Q&A with Bohr and Brad Heaney, the Ivy Bridge program manager. In addition to working together on Intel’s first CPUs using 3-D transistors, the two collaborated on Intel’s first processors using high-K metal gate technology.
“Being an integrated device manufacturer really helps us solve the problems dealing with devices this small and complex,” Bohr said in the Q&A.
I don’t doubt that for a minute. Since the dawn of submicron design, EE Times has been writing about the need for ever closer collaboration between chip and process designers. An Nvidia physical design exec underlined the same point in a recent talk at Mentor Graphics’ annual user group meeting.
But Bohr stretches the point too far when he says the foundries and fabless companies won’t be able to follow where Intel is going. I have heard top TSMC and GlobalFoundries R&D managers make a good case that 3-D transistors won’t be needed until the 14 nm generation. For its part, TSMC said at 20 nm there is not enough wiggle room to create significant variations for high performance versus low power processes.
I neglected to ask Bohr whether Intel has separate high performance and low power processes in its 22 nm technology. (Anyone from Intel is welcome to chime in here.)
However, in an open Q&A, Bohr said Intel has completed work on an SoC-specific version of its process technology. It plans going forward to have an SoC variant a quarter or two after each main process is complete.
For its part, Qualcomm would not provide its opinions on TSMC’s 20 nm plans. The company did say in its recent quarterly earnings call it can’t get enough 28 nm technology from TSMC to meet product demand, so it is working to develop multiple new sources it expects will come online later this year.
That’s a big opportunity for a GlobalFoundries, UMC or other fabs to step up. Given the close sharing of design details required to make 28 nm SoCs, it’s more of a risk than an opportunity for Qualcomm to work with Samsung’s foundry folks, Bohr said, given Samsung has its own Exynos mobile SoCs.
I asked Bohr to whom Intel is providing access to its 22 nm process besides two announced partners—Achronix and Netronome. He only said that Intel does not want to be in the general foundry business, but it makes its technology available to a few strategic partners.
Intel has no monopoly on smart process technology engineers and designers. But it does have some brilliant ones, and it has learned to market them smartly. Bohr and Heaney even appeared yesterday in another one of Intel’s playful videos shrinking the two engineers so they could tour the insides of an Ivy Bridge chip.
Looking ahead, Bohr said Intel has finished characterizing its next-generation 14 nm process using immersion lithography. It even has “encouraging results” suggesting it will be able to use immersion litho for the 10 nm node that is still in early planning phase.
“We think we have a [10nm] solution using immersion lithography—we’d love to have extreme ultraviolet [EUV] lithography, but we are not counting on it,” said Bohr in the event Q&A.
As a follow up, I asked whether Intel has other new process tricks like 3-D transistors at 14 and 10 nm. His answer: “Yes!”
I love it when companies celebrate and provide access to their top engineers. But I hate it when they are so well trained by their PR departments.
Skaugen (left) queries Bohr and Heaney (right) on their process/chip design collaboration.
A fabrication facility is costly to build. Foundry business and fabless will continue exist and work together to bring various components to the market.
Nonetheless, if design and production can work closely together like Intel, the company would have better competitive edge. The reason that Intel still push x86 based CPU into mobile market is they believe they can produce a low power consumption CPU using product technology. Let's imagine if Intel started producing its own ARM.
This is all hokum, and lot of smoke with no real fire. True Fabless won't work for all but the fact is it works for most and anyone thinking he can go from fabless to churning off sub 32nm wafers is probably out of his mind. Fab cost work to everyones advantage when its billions of dollars are amortized across billions of wafers.
Intel also would have gone fabless if they were not running a monopoly in PC business.
The foundry model is not affected by the technology status so much as the current business situation. It may help the foundries to consider IDM-type projects, just as IDMs are considering foundry-type projects.
Some companies can innovate internally, like Intel. Others cannot, even though they are big. A number of years ago, all jump on the band wagon to trash the ecosystem. Now that destruction is nearly complete. Those who cannot innovate internally may enjoy a hard earned collapse.
IDM versus foundry:
When asked if the multipatterning issues at 14-nm applied to both integrated device manufacturers (IDMs) and foundries Meurice said: "At 14-nm foundries have a challenge that the IDMs would not have. The challenge is that thay have to deliver design rules which are less restrictive and they have to deliver a shrink that is very aggressive." As such the decision to go to EUV for 14-nm concerns the foundry environment more than the microprocessor environment, Meurice said.
Could we be reaching the end of Moores law and technology shrinks in silicon manufacturing. Tri-gate might have mitigated the issues at the 32-22nm migration step but the fact that Intel had to resort to such a radical step is worriesome. What after that? 14nm? 10nm? Will tri-gate survive the shrinks?
If this is the end of the shrink race then this spells bigger trouble for Intel than the fabless makers. In order to keep the lead in process technology they will have to make radical changes to their manufacturing (read more complex lower yields, higher costs) and if they stumble or stop, guess what? All the minions of semi players will have a level playing field. Then it will be about who has the best design.
IMO, the reality is that one size/type of solution does not work right for all players. Fabless is great for some design houses, markets, and products, but not a good fit for others. Whenever we try to posit that one approach is "right" or "best", we are ignoring the engineering reality: it is all about managing and balancing tradeoffs and priorities, given your available resources and objectives.