The future of CMOS technology was center stage during the recent 2012 Symposium on VLSI Technology. The conference focused heavily on Intel's first technical disclosure of its new 22-nm Tri-Gate transistor along with issues like 3-D transistor design. A panel also explored FinFET device technology.
Surprisingly, there are vastly different views on the best direction forward. I have never seen a time in the industry where the views varied so much. However, it is possible that none of the experts are either right or wrong. It is very likely that each expert is using different "value metrics" which I define as some weighting of chip metrics (cost, power and performance) and chip design metrics (design cost, complexity and time-to-market).
Engineers are using different metrics since companies are targeting different markets. The two biggest markets for logic chips are, of course, mobile (smartphone and tablet) and PC devices. These markets are now steering the technology direction and defining the winners and losers. Even within a given market segment like tablets, companies use different metrics (some think the big tablet market is at a $199 price point (versus $499 - $999). As an educator with a five-tablet family, I tend to agree with the former).
For those stuck in their cubicle or fab back home doing real work, here are my top ten insights from the VLSI conference.
1.Intel's Tri-Gate is an impressive engineering feat. On a single 300-mm wafer close to a 1 trillion fins are fabricated (about 3 billion fins in each single CPU; each fin at the top ranges only about 6 to 9 nm in width which is only about 12 to 18 silicon lattice spacings). That would be the smallest lateral feature ever patterned with lithography to enter high volume CMOS manufacturing. Nearly each single fin is important to yielding a 22-nm CPU and a single broken fin would make the CPU unsellable. I continue to believe Intel is five years ahead of the industry with Tri-Gate technology.
2.Intel is currently shipping Tri-Gate CPUs, and though yield appears challenging most think Intel and its limited CPU offerings will be successful with Tri-Gate. In these ICs, performance has historically been valued over cost and power. However, the foundry and fabless mobile chip engineers are quick to point out that for mobile SOCs, there is no debate who has silicon technology and product leadership. Foundry 28 nm is far better on the chip metrics of cost, power and performance than the 32-nm technology used to fabricate Intel's mobile Atom processor chips (Medfield and Cedar Trail). Foundry also has a "rich" set of 28-nm IP design shipping, such as the integration of baseband and application processor on a single 28-nm monolithic SOC. I sense foundries and fabless companies were pointing that out in response to Intel's recent bold statement that the "Fabless Model is Collapsing!"
3.Before the conference, Intel's fin profile was reported by reverse engineering firm Chipworks to be trapezoidal, and that was one of the key topics before, during and even after the conference. Experts all agree that the ideal FinFETs should have a rectangular fin and yield issues likely drove Intel to alter the fin shape at the end of the technology cycle (potentially a tradeoff resulting from a schedule slip). During the Intel paper Q/A, the presenter (outstanding presentation by Chris Auth) was asked about the fin profile. Many in the audience were surprised that the answer was "performance" (lower external resistance). The leading hypothesis for the fin shape was that it is meant to fix a yield problem related to clearing the low k spacers material off the fins. The general consensus was that the fin profile (though fine for Intel) would have too much variation for mobile parts which are not speed or leakage binned (typically designed for > 98 percent yield at worse case speed and leakage variation). Most also thought that at 14 nm Intel would go back to a rectangular fin profile.
4.A general bulk trapezoidal FinFET (with single n and pFET work function and threshold voltage adjusted via halo doping design point) was also discussed. There was consensus on Intel's design point along with discussion of what lessons could be extracted from the interesting Intel work and applied to the mobile market:
a) There was a high degree of concern about the non-fully depleted transistor formed in the bottom, thicker part of the fins since it will cause an additional off-state leakage. Intel in its paper only reported leakage down to 1nA/um which is an appropriate CPU target, but mobile devices require leakage about 100x lower in the 10pA/um range for the always on and footer/header power gating devices.
b) Additional gate work functions would be another approach to lower off-state leakage. However, the complexity of doing four or more work functions (for just two threshold voltage types, 2n and 2p) on a 3-D structure was thought to be too costly and complex for the mobile market.
c) On the design side, the discussion centered on a bulk-only FinFET approach that would likely require system repartitions. The general thinking was that the power management unit, RF and even analog circuits would need to be off chip. For low cost mobile solutions, a single chip SOC is almost a requirement, thus FinFET would not be very attractive in the large middle range like the 3G SOC China market.
I think your right for market at large but I wounder if Samsung is close with this technology. They have been working on TSS for DRAM and FLASH. Might give them and apple a big performance and power advantage in app SOCs? Might be another area apple goes deep into supple chain like the did with mining special Al.
Borkor also nailed perhaps the biggest issue with sloped fins: oxide thickness variation.
Another quote form his journal paper.
"Unlike the planar MOSFET devices, the gate dielectric of FinFET devices is vertical. Its thickness and the Si/SiO inter- face are affected by sidewall SLOPE and roughness of the fin. We may expect some difficulties to get the same uniformity as the planar case."
In the Chipworks pictures, the gate oxide thickness does vary a lot fin to fin and even more within a fin. Much much more than Borkors 1-2A requirement. 10X more?
I continue to think design issues caused by transistor variation are not appreciated. . Author and even Borkor's paper did not talk about systematic variation with FinFETs but I just continue to be surprised by the outer to inner fin variation as seen in differences in the STI depth (see outer to inner fins STI depth). If I understand how this works most of my design would use between 1, 2 or at most 3 fins per transistor. Fin width being difference for 1,2 or 3 fin devices and Borkor's suggest this needs to be controlled within 1nm (=10 angstroms = 2 Si lattice constants?).
FDSOI has some advantages and disadvantages. The concept has been worked on in the industry for 15 years.
The biggest advantages are low leakage and low transistor variability.
The biggest disadvantages are lower pFET drive current (lower performance) since eSiGe is much less effective in mobility enhancement via strain and an easy method to adjust threshold voltage (SOCs require a wide dynamic range in Ion/Ioff which is achieved by threshold voltage).
I think your spot on. When I look at the product power reduction with 3D fins on 22nm Ivy bridge, it does not seem much if any improvement over a standard process shrink? Even if i use Intel numbers perhaps is an effective "2.2D" . Putting on my system architect hat, I think much larger power savings (as compared to 3D fins effective 2.2D) are possible with 3D Through Si via Stacking (TSS) between the DRAM and apps processor. I also think 28nm is the right node to introduce TSS as well.
Any process experts on TSS care to comment?
What makes 14 nm difficult could be the move to 3d fin transistor, that seems much more drastic than more pattern decomposition. And how about TSVs, for real 3D not 2.5, wouldn't it be easier to introduce at 28 nm rather than 14 nm?
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