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Intel forum is next front in x86 vs. ARM war

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EVVJSK0
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re: Intel forum is next front in x86 vs. ARM war
EVVJSK0   9/7/2012 3:58:08 PM
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Many software vendors are attempting to price their applications based on Cores (Physical and Virtual). Not so much right now on mobile, but that could be coming later. When talking about Servers especially, this could have a big impact on the price of an application implementation, especially if the direction of a server with a lot of cheaper, more power efficient ARM processors. It will be interesting to see how this plays out.

krisi
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re: Intel forum is next front in x86 vs. ARM war
krisi   9/6/2012 8:15:58 PM
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Kandou bus is an interesting wild card, but if they claim to be relying on patent pending technology what is likelihood of getting this adopted by standards?...I would rather license it for free and get my money by selling IP blocks. Here is some info (I am not paid by Kandou to disseminate this ;-) Kandou Technologies has developed a new patent pending approach to serial link design that increases the bit rate for a given physical communications link. With this technology more bits can be sent per unit of energy, or less energy can be used to achieve a given bit rate. For common high speed links, speed increases on the order of 400% or bus power reductions to 25% are readily achievable and will yield meaningful net design and manufacturing cost reduction as well. These gains are complementary, thus additive, to known advanced serial link design techniques in use today. The magnitude and potential for tradeoffs of these gains dramatically improves the constraint space across numerous aspects of the design of high speed electronic devices. Kandou Technologies has developed a new patent pending approach to serial link design that increases the bit rate for a given physical communications link. With this technology more bits can be sent per unit of energy, or less energy can be used to achieve a given bit rate. For common high speed links, speed increases on the order of 400% or bus power reductions to 25% are readily achievable and will yield meaningful net design and manufacturing cost reduction as well. These gains are complementary, thus additive, to known advanced serial link design techniques in use today. The magnitude and potential for tradeoffs of these gains dramatically improves the constraint space across numerous aspects of the design of high speed electronic devices.

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