One way to save Moore's Law from an unpleasant and industry-disrupting demise is for manufacturing process technology developers to make a series of changes at a given node – say 20-nm – but label each successive change with a smaller number.
In that way double patterning of deep immersion lithography can continue to produce chips that are in processes technologies that are labeled 16-nm, 14-nm, 10-nm and so on, thereby keeping Moore's law moving forward.
And as long as some feature on the chip can be measured at the
appropriate dimension it should be possible to find a way to justify the
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Of course, the IC die-area savings and cost advantages that we have become used to from previous process node transitions would not accrue with these forthcoming node transitions. However, as chip designers at the leading edge are becoming more interested in power savings than area savings as long as the successive process nodes produce ICs with lower power consumption all may be well.
David Patterson, known for his pioneering research that led to RAID, clusters and more, is part of a team at UC Berkeley that recently made its RISC-V processor architecture an open source hardware offering. We talk with Patterson and one of his colleagues behind the effort about the opportunities they see, what new kinds of designs they hope to enable and what it means for today’s commercial processor giants such as Intel, ARM and Imagination Technologies.