SANTA CLARA, Calif. – ARM will flex its muscles at its annual ARM TechCon here this week, an event to which I bring two questions.
One question is, what’s the deal on a 64-bit ARM core design? Last year, ARM announced at the event its 64-bit V8 architecture and Applied Micro tipped plans to design a custom core compliant with it for its X-Gene server SoC.
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Earlier this month, TSMC said it will validate its 16-nm FinFET process using an ARM V8 design. At the time, ARM suggested V8 products would start hitting the market around 2015. So, I fully expect to get some chapter and verse this week about exactly what this ARM 64-bit core will look like and when it might appear in products.
Incidentally, I also expect Applied will demo the first working ASIC version of X-Gene. And my colleague, Peter Clarke, expects ARM CEO Warren East will appear at today’s AMD press conference where there may be discussion of merging x86 and ARM cores in future AMD SoCs.
My second question is, what real value will big/little bring to mobile workloads that a single—say Intel x86 Atom CPU—can’t deliver? We heard a fair amount last year about ARM’s concept for pairing a mix of a Cortex or higher CPU with an ARM 7-ish core to achieve better performance per watt levels that either chip could do on its own.
Nvidia jumped on this bandwagon early with its Tegra 3 that uses four Cortex and one lower end ARM core to reduce energy drain in mobile systems. What’s not clear to me is exactly what sort of MIPS per Watt advantage such big/little designs will have over a straight Intel Atom.
ARM has a whole wealth of microcontroller-level designs that are proliferating in the embedded space from a variety of vendors such as NXP and others. If ARM really can leverage that to get to something an Intel Atom can’t deliver it would further distance the U.K. company from its archrival in Santa Clara. I don’t expect a microcontroller-level x86 from Intel anytime in the future.
No doubt there will be a few surprises along the way this week. We’ll be watching that microcontroller space, looking for any initiatives in the Internet of Things space, for instance.
Is ARM going to put all their eggs into one basket by backing 3D stacking of chips ( SoCs and Memory ) using TSVs ( thru silicon vias ) and wide I//O or would they be open to less disruptive ways to get higher bandwidth / power efficiency for their Core designs aimed at SmartPhones etc. ??
David Patterson, known for his pioneering research that led to RAID, clusters and more, is part of a team at UC Berkeley that recently made its RISC-V processor architecture an open source hardware offering. We talk with Patterson and one of his colleagues behind the effort about the opportunities they see, what new kinds of designs they hope to enable and what it means for today’s commercial processor giants such as Intel, ARM and Imagination Technologies.