Microprocessor analyst David Kanter makes some educated guesses on how Intel's 22-nm Haswell will perform based on an in-depth tour of the architecture.
SAN JOSE, Calif.--Want to know whatís inside Intelís next-generation microprocessor? Ask David Kanter. The CPU blogger just published a deep dive on Haswell, Intelís first chip designed for its 22-nm FinFET process.
Haswell will emerge next year, probably ahead of most of the 64-bit ARM chips and in tandem with AMDís next generation cores such as Steamroller. Ultimately, it will appear in everything from tablet SoCs to server CPUs.
Kanter describes Haswell as ďa dual-threaded, out-of-order microprocessor that is capable of decoding five instructions, issuing four fused micro-ops and dispatching eight micro-ops each cycle.Ē
At this stage, Kanter could only do a paper analysis of the microarchitecture. It will be many months before we see test results on working Haswell chips.
That said, Kanter was able to make some interesting high-level projections based on his deep dive into the workings of the chip. ďWe estimate that a Haswell core will offer around 10 percent greater performance for existing software, compared to [Intelís current] Sandy Bridge [processors, and] for workloads using the new extensions, the gains could be significantly higher,Ē he said.
In theory, some instruction set extensions could double performance on some jobs, and a new transactional memory feature could provide 30 percent gains on other operations, he said.
Measured next to its traditional x86 competitor, ďIntel is already far ahead of AMD in terms of CPU performance,Ē writes Kanter. ďThe performance gap should narrow given the scope of opportunities for AMD to improve, but Haswell will continue to have significant advantages.Ē
Haswell will come in 10W versions for tablets where it will compete with 4W ARM-based SoCs, Kanter added. We will need to wait for working silicon to know relative performance/Watt efficiency of Haswell against the ARM chips, he said.
Indeed, there will be plenty of tales to tell once real chips get out of the lab next year. Until then, microprocessor aficionados can enjoy Kanterís block-by-block tour of the architecture.
Perhaps a magic information fairy pointed him to an Intel Technology Journal Article
"TERA-SCALE MEMORY CHALLENGES AND SOLUTIONS"
And this corresponding patent:
"Systems, methods, and apparatuses for hybrid memory"
Sounds similar to what Huawei/Altera are doing and what I expect other comms and server OEMs will try out over the next year or so.
Haswell is going to be a 2.5 d module with the Level 4 cache chip next to the processor, the chips connected by fine-pitch high-density thin film interconnects on the Si substrate of the module. Will have lots of interconnects, enabling lots of parallelism in memory accesss by multi - core in CPU / SoC. BTW won't be able to stack chips ( true 3D ) because need to take heat out of the 10 watt CPU.
stacking memory on the CPU makes a lot of sense for any lower-power chip - after all, it's pretty routine in phones. stacking not only gives a performance boost, but saves some power. probably hard to do with a bigger/hotter chip, though.
10W is certainly workable for a tablet, as long as it can race to sleep, low leakage, etc.
I just wish AMD would grow some balls and produce, for instance, an APU with stacked dram so you could tile a bunch of them onto a board. whatever happened to the idea of scalable multiprocessor systems anyway? (with builtin scalable GPU for free!)
It's still a little rumor-like to me. I also saw Anand report it as embedded DRAM as if on-chip, but if it is off- chip, would they use TSV for the speed? Isn't the normal course to make it on-chip SRAM?
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