SAN JOSE, Calif.--Want to know what’s inside Intel’s next-generation microprocessor? Ask David Kanter. The CPU blogger just published a deep dive on Haswell, Intel’s first chip designed for its 22-nm FinFET process.
Haswell will emerge next year, probably ahead of most of the 64-bit ARM chips and in tandem with AMD’s next generation cores such as Steamroller. Ultimately, it will appear in everything from tablet SoCs to server CPUs.
Kanter describes Haswell as “a dual-threaded, out-of-order microprocessor that is capable of decoding five instructions, issuing four fused micro-ops and dispatching eight micro-ops each cycle.”
At this stage, Kanter could only do a paper analysis of the microarchitecture. It will be many months before we see test results on working Haswell chips.
That said, Kanter was able to make some interesting high-level projections based on his deep dive into the workings of the chip. “We estimate that a Haswell core will offer around 10 percent greater performance for existing software, compared to [Intel’s current] Sandy Bridge [processors, and] for workloads using the new extensions, the gains could be significantly higher,” he said.
In theory, some instruction set extensions could double performance on some jobs, and a new transactional memory feature could provide 30 percent gains on other operations, he said.
Measured next to its traditional x86 competitor, “Intel is already far ahead of AMD in terms of CPU performance,” writes Kanter. “The performance gap should narrow given the scope of opportunities for AMD to improve, but Haswell will continue to have significant advantages.”
Haswell will come in 10W versions for tablets where it will compete with 4W ARM-based SoCs, Kanter added. We will need to wait for working silicon to know relative performance/Watt efficiency of Haswell against the ARM chips, he said.
Indeed, there will be plenty of tales to tell once real chips get out of the lab next year. Until then, microprocessor aficionados can enjoy Kanter’s block-by-block tour of the architecture.
David Patterson, known for his pioneering research that led to RAID, clusters and more, is part of a team at UC Berkeley that recently made its RISC-V processor architecture an open source hardware offering. We talk with Patterson and one of his colleagues behind the effort about the opportunities they see, what new kinds of designs they hope to enable and what it means for today’s commercial processor giants such as Intel, ARM and Imagination Technologies.