The development of replacements for conventional silicon channel
material seems to have sparked a lot of work in this area. One paper
offers some results in terms of transistor performance achieved with Ge
channels and ZrO2 gate dielectric while another describes microwave
anneal techniques for Ge CMOS.
Another session combines imagers
and integrated sensor topics. If you have any interest in imager
technology, be it current or historical, then I recommend a presentation
from Panasonic, “Evolution of Optical Structure in Image Sensors.”
TSV technology appears poised for a commercial breakout, one paper from
Tohoku University in the Device Characterization and Reliability
session should be noted: “Minimizing the Deleterious Effect of Local
Deformation Caused by Cu-TSVs and CuSn/InAu-Microbumps in High- Density
In addition to the increased focus on interfaces with
newer device topologies and new channel materials, we also see renewed
interest in noise characterization of both types of new devices. Check
out this paper for more: “Insights in Low Frequency Noise of Advanced
and High-Mobility Channel Transistors.”
Finally, Marvell co-founder Weili Dai is speaking at IEDM’s inaugural “Entrepreneurs Lunch” on Wednesday (Dec. 12).
The paper on reliability discussing the "Effect of Local Deformation Caused by Cu-TSVs..." has important implications to the placement of TSV's and the keep-out rules. This is something that is still developing and has many process-dependent influences (via middle or via last etc.) as well as type of stacking (die to die vs. wafer to wafer) and the die thickness.
Regrettably I could not attend IEDM this year but would be great to see more review articles as Kris also comments above.
I am somewhat uncomfortable pointing this out, but the Stanford/Monolithic3D/Rambus IEDM paper (14.2) about heat extraction has absolutely nothing to do with TSVs. It talks about heat removal using inter-layer-vias of the Power Delivery Networks in monolithic 3D devices that have no TSVs. Just sayin'
David Patterson, known for his pioneering research that led to RAID, clusters and more, is part of a team at UC Berkeley that recently made its RISC-V processor architecture an open source hardware offering. We talk with Patterson and one of his colleagues behind the effort about the opportunities they see, what new kinds of designs they hope to enable and what it means for today’s commercial processor giants such as Intel, ARM and Imagination Technologies.