Simulations from a Scottish EDA company show that fully-depleted silicon-on-insulator process technology is the way to go at 20-nm, but better put the metal-gate in last not first.
The contentious issue of gate-first or gate-last in front-end of line (FEOL) chip manufacturing is raising its ugly head again; but this time in with regard to the fully-depleted silicon on insulator (FDSOI) process.
Some readers may remember that gate-first high-k metal gate technology was developed and touted by IBM's circle of chip manufacturing partners for the 32/28-nm bulk CMOS node. This was a contrast to the gate-last position taken by Intel, which of course went on to introduce the FinFET or tri-gate transistor at nominal 28-nm and 22-nm nodes. But IBM's bulk CMOS technology partners revealed that having gone gate-first at 28-nm they would move to gate-last at the 20-nm node.
Professor Asen Asenov, of Glasgow University and CEO of TCAD company Gold Standard Simulations Ltd. (GSS), has used its TCAD simulator to investigate the statistical variability in 32/28-nm FDSOI in comparison to equivalent bulk MOSFETs and studied the difference between metal-gate-first and metal-gate-last flavors of the technology. "Metal-gate-first FDSOI will be very good but metal-gate-last could be spectacular," said Professor Asenov.
But unfortunately nobody makes metal-gate-last. STMicroelectronics NV has started to offer gate-first FDSOI but so far doesn't seem to have much traction for the technology.
"Bulk CMOS has a problem of high variability; at 28-nm it is OK but at 22/20-nm it becomes serious. SRAM is most critical in terms of variability and SRAM is pervasive in SoC," Professor Asenov told EE Times. One of the tricks to make bulk CMOS work at 20-nm is to reduce the scaling of SRAM blocks but there is still a lot of leakage making 20-nm bulk CMOS power hungry, he added.
According to Professor Asenov's simulations FDSOI has advantages over both FinFET and bulk CMOS processes at the 28-nm node and beyond. This is because the reduced variability afforded by gate-last FDSOI means operating voltage can be taken lower before SRAM cells stop working. This opens up the range of voltage and frequency scaling that is possible and as power consumption is proportional to the square of voltage this makes a big difference in low voltage modes where application processors spend most of their time.
"The breaking news here is that if you can develop a metal-gate-last 28-nm FDSOI technology you will be able to achieve an astonishing SRAM supply voltage, in the range of 0.5 to 0.6 volts," said Asenov, in a statement. "Equivalent bulk at 28-nm requires approximately 0.9-V to secure the reliable operation of large SRAM arrays. Metal-gate-first FDSOI reduces the minimal SRAM supply voltage below 0.7-V and metal-gate-last FDSOI at 28-nm can reduce Vcmin even further to below 0.5-V."
That's the good news for the FDSOI camp. The bad news is that Professor Asenov reckons that they have still got the manufacturing process the wrong way round. STMicroelectronics' gate-first 28-nm FDSOI does match the gate-first bulk CMOS at 28-nm which makes for an easier transfer of libraries and intellectual property but is not the optimum configuration, according to Professor Asenov.
"I believe FDSOI is a very good candidate for low power but very few designs are being made at 28-nm. TSMC or Samsung could get a huge advantage by introducing metal-gate-last FDSOI, probably much better than FinFET at the same geometry," Professor Asenov said.
I am not sure I understand. What Asenov simulate is semiconductor device with a certain gate stack. In the simulator it doesn't matter whether the gate is processed first or last, it is just there. What am I missing here? Kris
P.s Disclaimer: I has been a while since I used Pisces, Medici or Silvaco's software, but the basic principle remains the same I think
It is about process: the following explanation is from Professor Asenov's blog:
In metal-gate-first the implantation and activation of the self-aligned source and drain result in the polycrystalisation of the metal gate. In the commonly used TiN metal gate the resulting average metal grain size is 5-6nm. It is believed that in the gate-last technology the metal gate, deposited after the implantation activation, will not suffer high temperature treatments and can be kept amorphous, thus eliminating MGG as a source of statistical variability.
thank you Tony...so the difference boils down to whether metal gate is amorphous or polycrystalline, right?...but I thought semiconductors can be amorphous, poly or mono but metals are metals, they can't be polycrystalline etc???
I think metals generally do have crystalline structure, but the grain size is typically very small. I think that during a high temperature anneal, there could be regrowth that you wouldn't get if you skipped the anneal.
However, I'm still not sure I buy the TCAD result. Advanced CMOS uses very short anneals to keep the junction shallow, and it's possible that clever engineering of stress films or dopant in the metal gate or something might impede recrystallization.
The issue is the variability of the structures.
Professor Asenov has extrapolated from bulk CMOS where it is the case that gate-last provides for less varitability in structures and therefore the ability to run devices over wider voltage ranges.
Data is starting to come in from LETI/STMicroelectronics that supports the superioity of gate-first FDSOI over bulk CMOS and Professor Asenov has been able to calibrate his TCAD simulation against some of that data.
But his point is that gate-last FDSOI should be even better and represents an opportunity for Samsung or TSMC or indeed any of the few companies that are left in leading-edge semiconductor manufacturing.