SanDisk Corp. (Milpitas, Calif.), a leading supplier of data storage products, has announced it intends to begin the transition of its flash products to 1Y-nm generation semiconductors in the third quarter of 2013.
The company is already producing high volumes of 19-nm based products, more than 50 percent of its output in 4Q12, although 24-nm flash memory will have a "tail" that will last throughout 2013, the company said in a recent conference call to discuss its 4Q12 financial results.
In fact SanDisk's announcement means that Flash Forward Ltd., a manufacturing joint venture between Toshiba and SanDisk with a relatively new Fab 5 300-mm wafer fab at Toshiba's Yokkaichi campus in Mie prefecture, Japan, will be making close the most miniaturized commercial integrated circuits in the history of the semiconductor industry. That is unless one of the few rivals, IM Flash Technologies, Samsung or SK Hynix can get there first.
The SanDisk roadmap has the 1Y-nm process lowering the cost of 128-Gbit memory ICs in 2013 and a 1Z-nm process taking monolithic memory to 256-Gbits in 2014. But judging who is most miniaturized all depends on how you define the 1Y-nm generation.
Over the last few years flash memory producers have started to become increasingly coy about declaring the minimum feature size of their processes. It started when one of the companies, I forget which, started talking of 30-nm class and 20-nm class manufacturing processes. By this the company meant a process with a minimum geometry between 30-nm and 39-nm and between 20-nm and 29-nm, respectively.
The other manufacturers quickly followed suit.
The psychology seems to be that if a company went public with the geometry detail before they got into volume manufacturing there would be concerns that a rival would somehow trump them and steal business. Of course once a product is out on the market it is possible for reverse engineering consultancies to cross-section chips and make independent assessments of the minimum geometry.
This is way of labeling chip generations is slightly different to the logic business where for each node a number is given but the nomenclature is becoming increasingly arbitrary. We have the prospect of 16-nm and 14-nm FinFET nodes coming in 2013 or 2014 that will use 20-nm back-end processes and are effectively 20-nm processes.
What we now know is that for Flash Forward, Toshiba and SanDisk, the 2X-nm node is a 24-nm node, while the 1X-nm node is 19-nm node. This would seem to put 1Y-nm at somewhere around 15-nm or 14-nm. That would give some room for the 1Z-nm generation to come in at 11- or 10-nm, which is now being touted as the last possible generation of NAND flash. We will see.
At the Q4 2012 earnings call, Sandisk CFO did in fact mention that they would get less cost improvement from 1Y nm (probably because it's from quadruple patterning) than from 19 nm in 2013, but they are still proceeding regardless.
I don't understand this secrecy about X, Y, Z...what exactly is 15nm is always debatable (which dimension you measure and how) so we might as well say as it doesn't mean much anyways...perhaps they are trying to borrow a page from the Apple book, let's be mysterious
David Patterson, known for his pioneering research that led to RAID, clusters and more, is part of a team at UC Berkeley that recently made its RISC-V processor architecture an open source hardware offering. We talk with Patterson and one of his colleagues behind the effort about the opportunities they see, what new kinds of designs they hope to enable and what it means for today’s commercial processor giants such as Intel, ARM and Imagination Technologies.