I've been writing about SerDes for at least four or five years now and I have always had an alternate idea about how to reconstruct its name from its nickname. Instead of Serializer-Deserializer, I think Serious Design (challenge) might be more appropriate from a design engineer's perspective.
You have the whole clock recovery problem to deal with, for example, as well as alignment complexity. If you're trying to handle a SerDes interface on an FPGA, you also have a huge chip area overhead and a considerably more expensive FPGA family to deal with.
Granted, SerDes is a solution to a very difficult problem: How does one move enormous amount of data on and off chip at rates of hundreds of megabits per second?
Still, the mission of top-flight engineers is to find a better way. And that seems to be what the people at Align Engineering have done with their Align Lock Loop (ALL) technology.
With this technology, each LVDS pair becomes a complete high-speed interconnect solution in a single clock domain (they use clock forwarding for alignment). Clock data recovery circuits are a thing of the past. So too are PLLs.
Such an elegant solution should be of interest to designers of wireless infrastructure equipment. For one thing, it would allow you to use cabling to analog data sources such as antennas.
So it sounds like a great idea. The proof is in the pudding, of course, so I will be very interested to know the results in a few months when Align transfers its technology to silicon and provides the demonstration we are all waiting for.
Align has just emerged from stealth mode but a bit more information is available at www.aligneng.com.