Today, IDT introduced a statistics engine that not only enables statistics tracking but results in packet processor cycles being significantly reduced (up to 90%) and an 87% improvement in QDR-II bandwidth.
Given the trend towards advanced services via IP-based networks, accurate statistics are becoming critical. Edge and access equipment needs to track thousands of customer flows well beyond NPU and ASIC capabilities and necessitating off-chip storage for counters. What is required is the ability to track statistics without compromising packet-driven operations.
IDT's statistics engine does just that. Based on an innovative "fire-and-forget" capability enabled by multi-port cell architecture, the device frees the processor of up to 800 additional cycles--better than 90%.
See the IDT announcement Statistics engine slashes packet processor cycles as well as a contributed article by IDT covering the use of statistics engines, Statistics engine reduces packet processor cycles 90%.
This one just may save a lot of time and money, while making a substantial dent in "best effort" networks.