Yesterday, my children Nicholas and Sasha and I spent hours at The Tech Museum in San Jose. Other than time out to experience an 8.2 magnitude earthquake (simulation), attempting hands-on microsurgery, and making Mr. Potato Head talk and turn on TVs and fans, we spent a great deal of time in the Internet section at the packet-processing display.
While their fascination centered on a display of the likely route packets would take, there is tremendous interest in a deeper level of packet processing issues. To address that interest, Network Systems DesignLine will host a NetSeminar entitled "Reinventing Packet Processing for Broadband/Access Box Designs" on February 16, 2006 at 1pm PT. You can register for the event at Register.
The panel is being formed as you read. Stay tuned for more info here and in the next two Network Systems DesignLine newsletters which can be accessed at subscribe to newsletter.
David Patterson, known for his pioneering research that led to RAID, clusters and more, is part of a team at UC Berkeley that recently made its RISC-V processor architecture an open source hardware offering. We talk with Patterson and one of his colleagues behind the effort about the opportunities they see, what new kinds of designs they hope to enable and what it means for today’s commercial processor giants such as Intel, ARM and Imagination Technologies.