A strict definition of Design-forManufacturing (DFM) requires a large scale modification of the EDA flow to enpower designers to be manufacturing aware throughtout the entire design process
In my blog DFM needs DFY I questioned the necessity of EDA vendors addressing the DFM market and the DFY market. separately. In fact there are companies that solely address DFM and others that only serve the DFY market. It seems to me, I said that DFM must be mindful of yield, so DFY should be a part of DFM and not a separate market or even a separate tool.
In his entry, posted through me, Gary Smith points out that my blog is talking about "the big definition of DFM", the Design For Manufacturing. In fact Gary says that what the EDA companies have implemented is "little DFM" what should in fact be called manufacturing aware routing or MAR. He goes on to say that a router that uses rule based DFM constraints while routing the IC is the most important tool today in this market. Magma and Sierra have announced theirs, while Cadence and Synopsys have not.
I agree with Gary's observation that to properly implement "big DFM" most of the EDA tools would have to be re-written, starting, of course, with those used to design (the D part of DFM) the IC. Once again I have been confused by Marketing, those people paid to take a wing and sell it to you as an airplane. Of course it may be an airplane some days, so why not call it that right now. It does save the costs of re-labeling.
When I was in engineering management, not too many years ago, I always tried to avoid rework by taking into consideration back end problems as early as possible. the strategy does save both time and money. Yet, the EDA industry seems to think that it is better to either just fix the problem in place and route, or even better, build a tool that fixes the routing after it has been completed. This of course sells more tools, even if it does nothing to increase designers productivity. The causes of poor manufacturability rest in the design, since the routing is the result of the design. One should be able to visualize the problem at the RTL netlist stage, even before synthesis. Yet, instead of doing an electrical analysis of the netlist, people wait until they have polygons and lines. The reason is simple: we do not have electrical characteristics for RTL representations. I fear we will need to wait for yet another startup.
To offer comments or differing opinions please go to the Forum area of this website and comment under the DFM/DFY topic.