Dave Goldberg joins Steve Glaser in calling for a redefinition of the term ESL.
I received this email following the publication of Steve Glaser proposal to redefine ESL in the HOW-TO section of this page. I seek and welcome feedback but I would encourage everyone to use the FORUM section of this page to send follow-up viewpoints. By using the Forum you will encourage real time dialogue instead of having your responses published asynchronously.
I'd like to respond to Steve Glaser's Commentary: Why its time to redefine ESL.
In his call to "redefine ESL", Steve Glaser has proposed a much broader and all-encompassing view of the system design problem. I applaud Steve's vision and his proposal to extend the definition of ESL to refer to the "Enterprise System Level".
While there are a growing number of EDA companies that have been categorized as being in the ESL space, many of these ESL companies claim to solve different aspects of the system design and verification problem by elevating the level of abstraction used for either design or verification. I'd like to think that a few of us are now offering more complete systems solutions aimed at increasing the productivity of the system teams, as opposed to simply targeting the C-based systems designer. While automated RTL generation is certainly an extremely valuable product of many ESL tools, it is not the only area in which ESL products can offer productivity gains.
Our customers often tell us that they value the verification automation of our solution as much as the ability to auto-generate RTL. They have given us the message, loud and clear, that an ESL design-focused generation technology must be accompanied by a strong verification strategy in order to support the system design effort, including both auto-generated verification IP, as well as the ability to incorporate the IP at higher levels of abstraction. As Steve mentioned, ESL products need to provide a more comprehensive solution for system teams, providing a wide range of support for system design, including analysis of design resources and options, verification and implementation, as well as addressing system-level issues such as software and hardware integration.
It is important to note that some of this support is already available today for system design team efforts, including:
- Full-featured verification support at the system level as well as the block level, allowing system design teams to leverage the power of reusing TLMs at multiple levels of abstraction.
- Verification support that fits seamlessly with a variety of verification environments, including vendor-agnostic simulation support, support for coverage metrics and other debug and analysis simulation utilities.
- A set of performance and resource analysis features that assist the user in design decisions and design exploration. These built-in utilities help the user generate good designs as well as efficient RTL:
Support for assertion-based verification and formal verification tools, including assertions to complement the auto-generated logic as well as pre-verified IP building blocks and protocol assertions to check for conditions like system deadlock and timeout.
Automated testbench creation with extensible corner-case generation capabilities.
Support for low-power design exploration and analysis as well as implementation.
Ability to fit seamlessly into a variety of backend RTL-to-GDSII design flows and methodologies.
Deep knowledge of backend physical libraries and process characterization data that is used for front-end analysis and implementation.
Software integration support in the form of automated generation of software driver code to initialize and manage tasks allocated to generated hardware.
A methodology for supporting a variety of hardware interfaces, allowing for integration in various system scenarios, including System-on-Chip designs and embedded processors.
- Interactive event-based queue simulation to help with FIFO/queue sizing and performance analysis and tradeoffs.
- Dynamic linting utilities.
- Visualization of computation and memory accesses to provide feedback derived from cycle-accurate traces.
- Simulation monitors designed to give high-level feedback and statistics about performance and events such as stalls, FIFO state.
As many semiconductor and design companies have engaged in strategic efforts to elevate their level of system design, some ESL solutions have recognized these demands and have evolved their products in order to provide a system team solution. While there's certainly more work required ahead, it's important to note that the depth and breadth of the currently available ESL solutions have evolved tremendously.
Dave Goldberg, Synfora, Inc.