The increased difficulty to economically develop leading edge integrated circuits from scratch and the shorter market windows for most electronics products first established and now supports a flourishing intellectual property (IP) market. In turn the use of IP blocks in system on chip (SoC) designs is proving a robust stimulus for using software blocks to replace hardware that is increasingly harder to design. In fact the percentage of silicon area taken up by firmware in chips manufactured below 100 nm processes is over 30% and raising monthly.
Heads in the Sand
And yet almost no EDA company is offering tools that address software design, development, and debug. The problem is that our industry originated, grew, and at times prospered in silicon. Many of our industry leaders have backgrounds in the semiconductors industry and even more built their careers solving hardware design problems. So, just as those who continue to insist that IP does not belong in EDA, those who now ignore firmware as an EDA issue are guilty of myopic views about the future of semiconductor devices.
Following established scientific methods, analysts have predicted that there is a very high probability that the percentage of a die area dedicated to firmware will surpass the 50% mark in the next two years. Since IP blocks will constitute the majority of the remaining area, it means that our industry will soon be dedicated to solving problems associated with a minority of the contents of semiconductor products. This does not bade well for achieving growth in EDA. When our products address the smallest portion of our customers designs, they will spend less money on them, with obvious consequences for the industry.
The high profile issues debated in our industry still have to do with silicon: design for manufacturing (DFM), design for yield (DFY), physical synthesis, are all developing tools that would allow engineers to reliably design new hardware using the latest manufacturing process. Jim Hogan, in a recent presentation on behalf of Ponte Design Automation as its Chairman of the Board, pointed out that there exist only five foundry conglomerates in the entire world, that will economically be able to produce 45 nm, and beyond, chips. The number of system houses using the latest manufacturing process, 65 nm, is smaller than anticipated and even fewer of them will use the next process node (45 nm). And yet the development of EDA tools to address the increasingly more complex design problems is becoming costlier wit5h dire consequences for EDA revenue.
Can you spell "firmware"?
The EDA industry tried to address the software/hardware integration issue by inventing electronic system level (ESL) design. As with all artificially created markets, ESL has struggled to find its customers. SystemC is ESL flagship product. And although the language has provided a good environment for hardware integration through its transaction level modeling (TLM) methods, and algorithmic evaluation through its C parentage, it has done very little for hardware/firmware development, debug, and integration. The reason is simple: SystemC does not address the needs of firmware development engineers and in fact creates obstacles to the real time debug of firmware.
Mentor Graphics has for many years had a division dedicated to embedded system design and development, but it has been the exception to the common profile of an EDA company. In addition, Mentor offers IP and also market emulators that address firmware debugging. Synopsys markets IP and has tried to address the firmware issue by providing firmware development platforms with its purchase of Aprio that allowed it to offer virtual silicon platforms for some commonly used microprocessor cores. With the exception of offering emulators, Cadence lags well behind its two largest competitors in firmware support and has no IP sales of its own. It is hard to find a startup in the valley that is addressing firmware development. The result that, since Nature abhors a vacuum, companies outside the EDA industry has increased their efforts to serve the growing firmware development market.
Programmable semiconductors companies like Altera and Xilinx have for many years developed their own tools to support users of their products. They have maintained that they cannot count on the reliable support of EDA companies and thus must develop products that are, at times, competing with those offered by traditional EDA vendors. Lately more than ever the EDA industry is proving them correct. ARM, the leading provider of IP blocks used in leading edge designs, is proving them right by increasing its development and marketing of proprietary tools aimed at supporting both hardware and firmware developers using their IP blocks.
And then there is The Mathworks. This company, almost unknown in EDA circles until two years ago, is more and more the shining example of what an ESL vendor should be. Instead of worrying about defining a segment of the system design market as EDA vendors have done (we only know electronics they stated), The Mathworks offers products that address the development of a range of systems, from communication to hydraulics, from automotive to aerospace. But it too had a limitation: The Mathworks products dealt with numerical analysis issues, providing tools that supported the implementation of algorithms using discreet numerical processes. And they too noticed that the amount of firmware used in system realization is growing. So, two weeks ago, they purchased PolySpace Technologies, a provider of embedded software (read firmware) tools for the automatic detection of run-time errors at compile time.
Do any of you think that such tools would not be useful in the development and debug of today's SoC devices? Could Mentor have made the same acquisition? Could any of its traditional competitors? Of course, but we still see the semiconductors industry as our main customer base, while the world is racing past building systems that rely ever more on software and specifically firmware.
What the near future looks like
Future SoC will be implemented using some or all of five major component types:
- Commercially available IP blocks
- Commercially available firmware blocks
- Proprietary reusable IP blocks
- Proprietary firmware blocks
- Proprietary unique hardware
Commercially available components can be designed to the most rigorous standards and the hardware portion will require the most advanced tools available, good news for traditional EDA companies. But few system and fabless companies will require them. Proprietary reusable blocks will need tools that will allow porting the design from one process technology to the next, and this too is good news for EDA companies.
But proprietary unique hardware, which will consume the smallest portion of any design will probably be done following relaxed design rules in order to meet both time and budget constraints and previous generation tools will be sufficient to meet engineers requirements. Cadence has already acknowledge as such by breaking its product families into two categories.
And firmware needs, which represent two fifth of the categories, are presenting only marginally served by the industry with no indication that the attitude is going to change. Even the latest book by Brian Bailey, Grant Martin, and Andrew Piziali "ESL Design and Verification" (published by Morgan Kaufman) falls in the trap of accepting present ESL definitions and limitations as its venue. The result is that discussions of firmware and its associated requirements are few while the majority of the book is dedicated to the methods of developing new hardware using ESL tools. This is not what most engineers developing SoC will be doing soon.
I expect that soon analysts will declare that Microsoft, ARM, and The Mathworks are the vital force behind the growth in the semiconductors industry.