Structured ASIC methods grow in appeal as process features shrinkwith every new process node.
Introduced a few years ago as a cheaper replacement to FPGA, Structured ASIC looked for a while as a quick success story for fabless semiconductors manufactures. In fact Altera found it necessary to come out with its own line of structured ASIC devices derived from its Stratix FPGA line just to make sure they would not loose designs initially implemented in FPGA to another manufacturer when the customer achieved volume production.
In fact the segment grew much slower than anticipated and a few startups looking for fame and fortune in this market quickly disappeared. But as development costs and design risks increase at leading edge process nodes, designers are looking for any method or tool that will allow them to meet requirements, schedule, and cost targets. And so, structured ASIC are gaining interest as an implementation alternative.
As ASIC designs move into the deep-submicron domain, timing, power and signal integrity issues become more complex. Increasing ASIC mask costs require customers to engage in extensive and expensive verification. Large non-recurring expenses, long turnaround times and minimum order quantities are, in many instances, an insurmountable obstacle for many design houses. So they have to adopt an older process and, almost always, scale down both performance and functionality of the product in order to adapt to the physical limitations of the process they have to use. Structured ASIC cells take away many of the problems associated with physical design of leading edge ASIC, since they are certified functional blocks that can be stitched together obeying fewer routing and placement rules than with custom designs.
I had been thinking about structured ASIC for the last couple of days, as I was planning this blog, and today, reading email just before writing this piece, I received an announcement of a seminar sponsored by Magma and eASIC addressing the use of structured ASIC. It is being held at the Santa Clara Convention Center on August 14th, from 11:30 to 1:30. You can go to the Magma web site to get more information about it.
Structured ASIC vendors are IP vendors when you really get down to the core of the business, and this does fuel the debate as to whether IP belongs as a segment of EDA or a segment of the semiconductor industry. But, when you really think about it, are fabless semiconductor companies really semiconductor companies? Many of them provide everything you need to design and bring to manufacturing your device, but someone else creates working silicon and someone else generates revenue from the manufacturing process. Most of what fabless semiconductor companies do is electronic design, not semiconductor manufacturing. Care to split more hair?