The presenters at CICC are pointing out that some ofthe problems found at very-deep-submicron processes can be solved at the architectural level.
The Custom Integrated Circuit Conference (CICC) going on at the Doubletree Hotel in San Jose, California is the type of show my friend and mentor Bill Schweber (editor of PlanetAnalog) would enjoy. You could really call this conference the circuit design conference, since the majority of the attendees (450 to 500 this year) are mostly analog circuit designers. The conference, according to its Chair Ann Rincon of AMIS, is slowly expanding its technical program to include more digital tracks, but most of this year's technical sessions deal with circuit design issues.
Papers presented at the conference are divided into two major categories: those that are part of the technical program and those that are poster offerings. The Program Committee has a simple way to classify a proposed paper in one of the two categories: if you can demonstrate that you have implemented the subject of your paper in silicon, you are eligible for inclusion in the technical program, else your paper is presented as a poster during the exhibit times. This year I counted 26 invited papers. The Technical Program Committee invited researchers and developers who have attained a certain notoriety in a specific field to write, submit, and present some aspects of their work.
I have been surprised by the lack of participation of EDA vendors at the conference. Cadence gave one tutorial and is presenting two papers and Synopsys has a booth during exhibit hours. Solido and Nascentic also exhibit, but both Mentor and Magma are absent, and so are all the individual DFM tools vendors. I see the conference as providing a very good opportunity for discussion of design and fabrication issues facing both analog and digital designers, especially if using or planning to use 65 or 45 nm process nodes.
If there is one message I brought back from the conference is that just scaling the same circuit you had at 90 nm for 65 nm will not work. Leading edge processes are demanding fresh approaches, including forgetting the traditional division between digital, analog, and software implementation. As Dr. Young of Intel stated during the Monday afternoon panel, you need to think hybrid, you need to become a digilog engineer. Other speakers repeated the message: solve manufacturing issue at the architectural or design stage, do not wait until just before place and route.
May be one of the reasons ESL has been so slow to take off as expected is because you never see the word analog and ESL written, not just in the same sentence, but in the same paragraph. So now you have seen it: proper ESL should allow designers to experiment and trade-off among digital, analog, and software solutions. And that would be real system level design.