On Tuesday October 9th, Cadence hosted a web seminar for members of the press. Four editors declared their presence, including myself. In addition to Cadence, ARC, Freescale, Fujitsu, and TSMC were represented. Si2, as the administrator of the Open Power Coalition also gave a status report.
As the creator of the format, Cadence has done a very good job in integrating all of its tools that deal from RTL to silicon in the CPF flow. This fact was reflected in the presentation given by Milind Padhye, low power design manager in the Wireless Design Group at Freescale Semiconductor. He did not specify if CPF was used in a production design or a test design. But he did report that the design team felt that the low-power intent for use during design verification was well supported by CPF.
Tatsuya Nakae, senior staff manager at Fujitsu Microelectronics America presented the results of a 90 nm low power test chip design his group undertook. Although one can specify a test chip to identify very specific areas not commonly found in the aggregate in a real chip, some of the findings were interesting. In particular the Cadence flow properly inserted level shifters, isolation buffers, always-on buffers, and power switches automatically without the need for modifications in the original RTL description. The results were that multiple supply voltages and on-chip power gating circuitry were implemented successfully. The report suggested that the chip development took two to four weeks longer than what had been anticipated based on previous experience with chips of similar size. Mister Nakae commented that the time penalty was justified by the quality of the results and was, therefore, acceptable.
Tom Quan, director of EDA and design services marketing at TSMC North America described how Cadence CPF low-power flow is supported in TSMC Reference Flow 8.0. His presentation did not make any reference to the Synopsys UPF low-power flow which is also supported in the same Reference Flow 8.0 environment.
While the other presenters all worked exclusively with Cadence tools and CPF, Gagan Gupta, director of product marketing at ARC described how his company, in conjunction with Cadence and Virage Logic, developed a flow that uses CPF but pays attention to the software component of the system. At this time, CPF does not offer any support for neither architectural design nor software development and debug, so ARC uses two of its products, ARChitect and Energy PRO to supplement the flow. The lack of support for any abstraction level above RTL was mentioned by a number of speakers as a weakness of CPF and something that needs to be addressed.
Steve Schultz, president and CEO of Si2, said that although it may be possible to unify CPF and UPF there were no active steps being taken at this time. He contributed the fact that the OPC working group had finished a comparative study of the two format and that the report was available to all interested at: http://www.si2.org/?page=866.