IMEC, as reported here, has announced its intention to open a 3D-SOC design program. It is clear that 3D integration can go a long way to mitigate some of the problems plaguing IC designers using processes more advanced than the 90 nm node. Multiple die system-in-package would diminish power requirements and thus mitigate thermal issues, and would also allow more independence from process nodes by allowing the integration of die fabricated with different processes in the same package. One can theoretically envision one package containing a memory die fabricated at 45 nm, a processor at 65 nm, and an analog circuit at 180 nm. Of course the problem is how do you fabricate the interconnections between the dies.
During the panel presentation of the new initiative, speakers observed that they did not expect much help to come from the "big three" EDA companies. In various columns in the past I have often stated that EDA cannot be expected to behave in any other way than a traditional market. Supply will meet demand, but without demand there is no reason for EDA to supply solutions to future problems. If the electronics industry expects EDA companies to lead in the generation of markets, then a new financial model must be developed to reward leading edge development.
To be sure the market for 3D multiple die system-in-package does exist, but it is too small yet for the "big three" to address. Micro Magic has recently announced a 3D layout tool, MAX-3D that addresses this market. You can read about it here. Magma, although excluded from consideration be the IMEC panelists, has just acquired Rio Design Automation in an effort to gain expertise in the area of packaging and package interaction with both the die and the board. Mentor Graphics and Cadence also have expertise that can be used in developing solutions, while Synopsys at this point lacks an in-house group dedicated to packaging issues. Zuken has long been a pioneer in 3D issues, but its presence in the American market is quite small.
The challenge for Mentor is to find a way to foster collaboration among its Deep Submicron Division, the Design-to-Silicon division, and the Systems Design Division. Mentor's divisions are rewarded based on their individual performance, not on how well they play together. Who would own such a tool? The Systems Design people because the package ultimately is integrated on the PC board, the Design-to-Silicon division because they have the DFM capability, or the Deep Submicron division because they understand the physics that make the design of the device possible in the first place?
Cadence has less of a structural problem, since Jim Miller controls all of the product organizations, so there is a common motivator that can foster cooperation. What seems to be clear is that Synopsys may want, once again, obtain PC Board expertise, since a system is a system, regardless of the nature of its parts.