Steve Bailey, General Chair of this year's DVCon conference, announced that both attendance and exhibition square footage have surpassed last year's figures and set a new record for the event.
Steve Bailey, General Chair of this year's conference, announced that both attendance and exhibition square footage have surpassed last year's figures and set a new record for the event. Sponsored by Accellera, the conference offers to design and verification engineers an opportunity to share experiences and learn new techniques used in actual design projects.
The success of the conference is an indication of both the importance that verification plays in electronics product development, and the fact that a focused three days event can achieve both technical and financial success, contrary to the experience of some larger conferences that have seen attendance figures decline recently.
Technical Program for the Practicing Engineer
Over the span of three days, February 19 - 21, attendees had the opportunity to choose among five half-day tutorials, thirty papers, and three embedded tutorials. In addition, the North American SystemC Users Group chose to co-locate its meeting with DVCon to give its members the opportunity to attend sessions relevant to their design and verification interests, as well as expose the conference attendees to the latest development in SystemC methodology.
The five tutorials held on Tuesday were attended by almost five hundred engineers. Topics covered ranged from Open Verification Methodology (OVM), Formal Verification for Advanced Users, an Introduction to the OSCI TLM-2 Draft Standard, and two tutorials presenting different techniques for Assertion Based Verification, including one specifically dedicated to issues in low power designs. Of the ten technical sessions in the program, only one was dedicated to academic research, while the rest covered design and verification issues that engineers face in their daily work. Attendees can see how papers on theory presented at more academically oriented conferences transform into papers on applications, signaling adoption of new tools and methods by the industry.
Due to time constraints only one of six proposed technical panels could be included in the program. The session, held on Thursday morning, provided the panelists with the opportunity to share their views on the present use of formal verification methods and tools.
The vast majority of exhibitors stated that they were very satisfied with the quality of leads collected during the exhibit hours, due mostly by the self-selecting profile of the attendees. The exhibits floor was open for only six hours over two days, Tuesday and Wednesday. Both sessions were sponsored, by Synopsys on Tuesday and OVM (Cadence and Mentor) on Wednesday, offering snacks and beverages to the visitors.
Keynote Speech Acknowledges Progress in Verification
Dr. Walden C. Rhines, Chairman and CEO of Mentor Graphics, delivered the keynote speech on Wednesday afternoon. Speaking on the topic: Ending Endless Verification, Dr. Rhines compared the evolution of IC test methods with that of verification methods. The challenge is the same in both cases: increased complexity of what needs to be tested versus the efficiency and sophistication of tools and methods available for the task.
As test methods developed from functional tests to built-in-test methods, to methods to avoid redundancies in test vectors, engineers have successfully solved the problem. The adoption of the latest method has resulted in improvements of two orders of magnitudes between 2001 and 2007. Dr. Rhines reported that the ITRS (International Technology Roadmap for Semiconductors) is predicting that another order of magnitude improvement is possible by 2013 resulting in tests that are a thousand times more efficient in the span of just over ten years.
Dr. Rhines then pointed out that verification methods based solely on functional tests are compute intensive and without a change in methods it will soon be impractical if not impossible to fully verify a design. It is therefore necessary to adopt new verification methods. Emulation technology and improvements in simulation technology as well as the adoption of formal verification tools have provided approximately one order of magnitude in verification efficiency.
Dr Rhines said that we must find a method to stop verifying what we have already verified by using a combination of intelligent test benches, formal methods, and transaction level modeling. Early results in the use of intelligent test benches have shown improvements around two orders of magnitude over traditional methods, and the other two methods are promising similar kind of results. What is exciting is that these three methods are not mutually exclusive, in fact they can, and should, be used together. A verification strategy that takes advantage of all three techniques results in a higher level of test coverage in a shorter period of time, making full coverage possible in a practical amount of time using economically feasible compute resources.
The Troublemaker's Panel
On Wednesday afternoon John Cooley presented his now traditional Troublemaker's Panel. This year the event was mostly informative and devoid of confrontational episodes (at least involving members of the panel that were actually present on the stage). Cadence was the only major EDA vendor that chose not to send a representative to the panel.
Based on questions suggested by subscribers of John's DeepChip mailing list, the panel explored a number of issues. Unfortunately most of the questions had nothing to do with verification, since this is not the most important issue discussed on the DeepChip Web site. As is his style, John delighted on the fact that Cadence was not part of the panel and fired a few gratuitous remarks in their directions. I personally find it in poor taste to discuss specific company issues in a one sided manner within the context of a panel. Some of the remarks were clearly intended as entertainment for the audience and had absolutely no informational content.
The questions ranged from whether or not the use of SystemC is growing signaling the adoption of ESL methodologies by designers (it is according to Brett Cline and Gary Smith), to the impact of present immigration policies on the growth of the electronics industry in the United States. All panelists agreed that American universities are not graduating enough engineers to satisfy the requirements, and given the restrictions on immigration, companies have no other choice than moving design activities offshore.
Panelist also agreed that significant improvements in analog design methods are required in order to sustain the demand for consumer products. Both Synopsys and Magma, together with a couple of startups, are rumored to be very close to the introduction of their own analog and mixed/signal design tools that will compete directly with Cadence's Virtuoso product that has so far enjoyed a practical monopoly in this market segment.