According to market research firm Gartner Inc. FPGAs now have a 30-to-one edge in displacing ASICs in design starts. The firm predicts the trend in 2009 will be exacerbated by the global financial crisis.
Gartner said the financial crisis started to take its toll on ASIC design starts in the fourth quarter of 2008 in the form of push-outs of design projects into 2009.
Since most ASIC vendors have a design cancel fee, there will likely be no word of them being canceled, Gartner said. But just how many of these designs will never go forward is a key question.
At the Embedded Systems Conference, Atmel took the wraps off its newest CAP7L metal customizable MCU that allows ARM7-based SoCs to be implemented with 12 week turn-around, a nominal NRE charge of only $75,000, and unit costs as low as $5, including the ARM-license.
According to Jay Johnson, Atmel's director of CAP marketing, comparable low-volume SoC implementations typically have up front license fees for the ARM core that start at $100,000, as well as unit costs of $100 or more.
AT91CAP7L devices are standard product microcontrollers with up to 200K gates of metal programmable cell fabric that can be used to implement proprietary customer IP, hardware accelerators, additional processor cores or unique peripherals sets to achieve a customized SoC.
Johnson added that the "secret sauce" implemented in the FPGA is vulnerable to theft. In many cases, it is not an option. "Fabless semi companies can not go to market with an FPGA solution," he said.
Meanwhile, Xilinx Inc. president and CEO Moshe Gavrielov presented data on the trend of declining ASIC starts at a product launch this February. He correctly predicted what has been known for some time: FPGAs will dominate for many applications while traditional gate arrays and structured arrays are relegated to high-volume tasks.
New opportunities always present themselves in the midst of an economic recession.
Shoot me a note on your experiences using ASICs and FPGAs, and whether the tools are adequate for either.