Potential catastrophic failures from ESD can have large positive effects on yield and performance but at the same time complying with new verification rules is difficult and time consuming using conventional approaches.
A joint research team from Infineon Technologies and the Indian Institute of Technology, Bombay, is claiming an advance in the integration of high-voltage functionality for advanced CMOS technologies.
The joint program, launched in 2007, focuses on advanced research into the areas of I/O device design and multi-gate MOSFETs for sub-45-nm node CMOS technologies.
"The collaboration has been very helpful to us in understanding the complex nature of some of the existing device reliability issues, and the solutions proposed significantly improve our products," said Harald Gossner, senior principal engineer for ESD research at Infineon.
Hazem Hegazy who works at Mentor Graphics in Cairo, Egypt states in an earlier technical paper said that complying with electrical rule checks that address reliability issues caused by crossing multiple power domains and potential catastrophic failures from ESD can have large positive effects on yield and performancebut, at the same time, complying with these new verification rules is difficult and time consuming using conventional approaches.
Hegazy claimed that being able to program electrical rule checks is one more step on the ladder to tackling increasing circuit verification challenges, on both the geometrical and electrical side.
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