It's generally acknowledged that we have entered the 45 nm processing node era. It's also well known that at this node the mantra among SoC designers should be "verify!, verify!, verify!"
IP provider Virage Logic Corp. this week announced that since being named TSMC's 40-namomenter early development partner in 2007, the company has seen strong adoption of its extensive 40nm product portfolio.
Comprising embedded SRAMS, embedded memory test and repair, logic libraries, and memory development software, the company's silicon-proven 40nm product offering has been designed to optimize area, performance, power and yield.
Virage claims that today more than ten customers rely on Virage Logic's 40nm product portfolio to design more efficient chips more quickly and with less risk as they develop products for such end markets as graphics, consumer, enterprise, networking, wireless, and handheld.
"TSMC selected Virage Logic as an early development partner at 40nm as a continuation of our collaboration in technologies ranging from 250nm to 40nm. Virage Logic and TSMC work closely to qualify IP through both Virage Logic's procedures and TSMC's procedures including silicon validation of these advanced technology IP solutions," said Dan Kochpatcharin, deputy director, IP Portfolio Marketing at TSMC. "These extensive silicon quality report results are available to designers of advanced SoCs for review when choosing Virage Logic's broad IP portfolio on TSMC's 40nm process."
That seems to settle it.
Unless you start listening to the verification guys. Rajeev Ranjan, Chief Technology Officer at
Jasper Design Automation says in an upcoming EE Times Viewpoint: "What is indisputable is that all today's conventional verification tools are proving insufficient as we head toward 45nm designs; and building faster and larger compute farms and utilizing specialized hardware is not the answer. New methodologies and technology are needed, and quickly, to address the challenge."
Ranjan is pushing the technology Jasper is known for: formal verification. The company has accumulated an impressive number of patents in the formal verification field.
He claims that over time formal verification has attracted a broad audience: "Over the past five years, formal verification was deployed first by experts in the verification team, then by the entire verification team, and lately it has been spreading to the designers themselves."
He contends that formal verification can mitigate risk at several stages of the 45nm design flow.
"To check the IP block for all possible configurations, formal technology can perform analysis and also check for compatibility amongst different modes of operation. The latest formal advances can check the correctness of programming sequences used to configure the IP blocks and can also help generate efficient programming sequences from scratch," says Ranjan.
So while the system-on-ship designer can obtain the latest IP blocks from Virage Logic, verifying that the IP block will work as prescribed in the final SoC requires trust in the adopted verification tools and methodologies.
Jerry Frenkil, Sequence Design CTO, refers in another upcoming EE Times Viewpoint to his company's power verification approaches. But the mantra he applies to power verification can just as well be applied across the board to all verification design flows: Instead of using a "trust but verify" a better approach to verification is to start early and "verify, verify, verify."