A crisis should never go unused and is an opportunity to put incremental changes to one side and think fundamentally about how to change things for the better, to rethink everything for recovery readiness.
That was the gist behind Synopsys' chairman and CEO Aart de Geus remarks to the San Jose Synopsys User Group this past March.
The recession has the semiconductor industry in a chicken-and-egg bind: chip companies can't predict where their next orders will come from and long manufacturing lead times make it difficult to respond quickly to new orders when they come.
Here are my ten talking points I came away with from the remarks the Synopsys chairman was making:
The current downturn is similar in scale to the 2001 downturn, which was by far the biggest in semiconductor history.
Most semiconductor experts think chip sales will stabilize and probably plateau somewhere between 30 and 35 percent down from its September 2008 level.
It's clear that the current recession will have a major impact on the future of the whole industry.
Chip companies are moving to a fabless (or fab-lite) business model.
The recession is forcing design teams to focus on profitable design.
40/45nm process design starts have already started to level out, while some design teams are competing to get to the latest 28/32nm process nodes for their most advanced designs.
Design teams are still targeting the older nodes: there are potential cost benefits for those that can use well-proven, existing technology. However, getting the last cent out of each chip using 90nm and 130nm requires some very advanced design.
Non-recurring engineering (NRE) costs are growing rapidly, especially for verification and synthesis.
To ensure there is a return on investment in chip design, the EDA industry must continue to rein in the cost of design, so that $100m design costs don't become the norm.
Semiconductor companies are now hiring similar numbers of software and hardware engineers. Designers have to work together to integrate hardware and software, and most importantly, verify it together or in parallel.
Oh, and by the way, engineers need faster, higher throughput and more thorough verification to satisfy the demands of growing hardware and software complexity.
Look for the upcoming EE Times July 13 issue where a report on "EDA at the crossroads" will feature viewpoints by industry participants. I'd like to hear from you of your experiences using design tools to make your chip designs successful on first tapeouts.