A dramatic shift is taking place in the technical conference area: provide an entire design-oriented conference and exhibits to millions of desktops across the globe.
Recently, TechInsights, the media company behind EE Times, has embarked on a virtual conference trail. The last two conferences, on Multicores and on Power Management, are now archived.
The next virtual conference is on the System-on-Chip challenges, scheduled for Sept. 16, 11 am to 6 pm EST.
Two keynote presentations will reflect the alternative SoC implementation flows. In Deriving ROI from Next-Generation SoCs, Magma Automation CEO Rajeev Madhavan will discuss what it takes to make a modern ASIC-based SoC design profitable.
In his talk, Design Innovation Beyond SoC, Gerry Gaffney, President of Altium, USA, will discuss the design approach and tool systems needed to exploit the full potential of FPGA-based SoCs.
Scheduled chats, panel discussions and web seminars throughout the day will be on such topics as Verification and Intellectual Property.
Verification is the single biggest challenge in the design of SoC devices and reusable IP blocks. One way to address this challenge is to adopt a reuse-oriented, coverage-driven verification methodology. In the case of ASIC-based SoCs, the Verification Methodology Manual (VMM) for System Verilog jointly authored by IP provider ARM and tool vendor Synopsys is just one methodology.
A panel of experts on verification will inlcude the following experts: Brian Bailey, independent consultant; Janick Bergeron, Fellow, Synopsys; Nick Heaton, Senior Architect, Cadence; and Tom Sandoval, CEO, Calypto Design.
The chip economics panel will examine the state of the economics of different forms of SoC design, delve into specific areas of increasing costs (verification, etc.) and try to ascertain whether there is any relief on the horizon.
Moderated by Dylan McGrath, West Coast Online Editor, EE Times, the panelists include:
Grant Martin, Chief Scientist, Tensilica, Inc.
Ron Collett, Co-founder, President and CEO, Numetrics
Sven Andersson, ASIC FPGA Designer, Realtime Embedded AB
Steve Douglass Vice President, Product Development, Xilinx, Inc.
The full program of the SoC VC can be seen here. It's being managed by Clive Maxfield.
Archived VCs can be found here.