PARIS The countdown to the 47th Design Automation Conference (DAC) in Anaheim, Calif., has begun. Before you get to the Convention Center, have a look at EDA DesignLine's list of EDA products that will be introduced and showcased at the show.
Note that a host of product announcements are still under embargo. The list will then be updated as new information arrives.
And, obviously, company names, mostly EDA startups and SMEs, are presented in alphabetical order.
- C -
- Calypto Design Systems, Inc. said it will demonstrate the latest version of its SLEC functional verification solution that formally verifies equivalence between ESL models and RTL implementations.
The SLEC 5.0 release, Calypto claimed, includes technology for verifying deep, complex loop structures in ESL flow.
- ClioSoft Inc. announced it will be introducing Visual Design Diff (VDD), which is said to enable users to "quickly and easily" compare two versions of a schematic or layout by graphically highlighting the difference directly in the design editor.
VDD is tightly integrated with Cadence Virtuoso 6.x (OpenAccess) and 5.x (CDBA), and can be used whether the Cadence user has the ClioSoft data management system, another data management system, or no data management system at all.
- At this year's DAC, French ESL company CoFluent Design (Nantes, France) said it will present a pre-release demonstration of the embedded C code generation feature in its CoFluent Studio ESL modeling and simulation software environment. CoFluent Studio generates C code for the IEEE POSIX standard.
- Compaan Design BV (Amsterdam
The Netherlands) said it will release the Compaan HotSpot Parallelizer for ISO C, supporting x86-multicore runtime verification and Xilinx FPGA code generation. This product integrates Compaan Design’s parallelization, streaming and mapping technology with ACE’s industrial quality CoSy compiler development framework.
The Compaan HotSpot Parallelizer translates C-code hotspots to data streaming Kahn Process Networks that utilize highly parallel heterogeneous multicore chip architectures, the company added.
- Coventor Inc. (Cary, N.C.) announced it will showcase its MEMS+ product line, a full-featured MEMS design platform that is specifically designed to integrate with traditional analog and mixed-signal IC design methodologies and tools, and shield designers from the complexity of MEMS design.
- D -
- Design and Reuse SA (D&R) (Grenoble, France) said it will demonstrate a third generation platform that now features a Documentation Management System around a Data Viewer where company members can Search, View On Line complex hierarchical product documentation as well as Download on Demand any specific documentation configurations.
The so-called “XML Packaging Station” embedded in the platform allows to enter documentation data through XML links and to store the documentation in a repository under revision control, the Grenoble-based company noted.
- Docea Power SAS (Moirans, France) said it will demonstrate Aceplorer 2.0 and AcePowerModeler.
Aceplorer 2.0, Docea claimed, adds project management capabilities to boost productivity and a link to virtual platforms to assess the impact of complex scenarios and embedded software on a system’s power consumption.
The company will also preview AcePowerModeler, a power model generator tool that closes the loop between implementation and architectural modeling by automating the creation of power models from lower level simulation and characterization data.
In parallel, Docea and CoFluent Design (Nantes, France) said they will provide a prototype demonstration of the interoperability between CoFluent Studio ESL modeling and simulation software environment and Aceplorer (ACE stands for Abstract Concept of Energy).
A third element of interest is the demonstration by Docea and Paris-based Magillem SA of a power-aware platform description based on IEEE 1685IP-XACT on June 14 and June 15.