Below is an excerpt from Mike Dini's most recent newsletter.
It has been a bad few weeks for FPGA startups. Tier Logic and Abound Logic (M2000) closed the doors, both apparently unable to get funding to continue. After some prodding from several high tech journalists, some bloggers, and a slew of calls from investor/wall street types, I started looking into the Tabula FPGA technology. Tabula is yet another FPGA startup. They kind of came out of stealth mode in March’10. Of them all, they are most richly funded, with $106M invested to date. And they need more.
With the possible exception of Mathstar, I have never worked so hard at trying to figure out how a new type of programmable technology works and how it should be applied. Tabula has come out of stealth mode, only to remain stealthy. One mask came off, revealing a different one. There are simply no coherent technical details to be had and Tabula isn't talking. After studying the available documentation, I cannot even determine how many equivalent flip-flops a given Tabula FPGA contains, let alone if the technology is useful. I can give you a range, but no number to within a factor of 8.
Worse, Tabula has no example RTL implementations of, well, anything. The devices appear to be slow, even in the 40nm TSMC process. Also, they appear to be relatively small, maxing out at 1-2M equivalent ASIC gates. This is comparable to Spartan-6 and nowhere near the larger Xilinx Virtex-6 or Altera Stratix-4. Worse, the technology will consume more power due to the massive amounts of context switching involved. The price points presented to us where OK, but not mind blowing.
Regarding the structure, rather than making a two dimensional FPGA as do all other FPGA vendors, Tabula has some magic ‘fold’ that is reconfigured up to 8 times per clock cycle. This mysterious ‘fold’ consists of something less than a 4-input LUT and one, or more, transparent latches. Clearly some routing is thrown into the mix, but how much and its structure is proprietary. The latch holds the interim logic result while the fold and routing are reconfigured. They have added ‘time’ as a third dimension by rapidly reconfiguring the same basic logic block. Frankly, this isn't terribly clever, but they do come up with some cool new Latin-based terms.
The devil here is in the details and implementation. They claim they can do the folding trick with the tools while hiding the details from the FPGA developer. This claim is so silly it makes my teeth itch and represents high-tech marketing at its most repugnant. If my design doesn't meet timing and I know nothing about the underlying architecture, how do I fix my problem? Assume a LARGE amount of technical support will be necessary.
At some point in the life of an FPGA startup, the target of your pitch changes from investors to engineers. Tabula has not yet made that transition. I'm not optimistic about this technology.
Mike Dini is President of The Dini Group (La Jolla, California). To read more of his newsletter click here.
No big deal really. Tabula's space time technology is nothing more than serially reading out pages of a config ram. Consider a N x M array of ram bits. These bits configure a basic LUT just like Xilinx or Altera config rams. Now imagine 8 of these N x M ram arrays grouped together. Normally to read out 8 different pages require a 3 bit select. But obviously you can also do it with 8 serial decoded page select bits. Having 8 serial bits means a 8 bit page select register which can shift at multi Ghz speed to select each N x M page in sequential order. Easy when it's just a 8 bit shift register. So each of the 8 pages are sequentially read out of the config ram to reconfig the LUT to do a different function. Now obviously you need some FFs to hold the value or context of the previous page of config ram while you shift to the next one. Of course, the big trick is how to map a Verilog or HDL design into sequential paged logic. But the solution is not that hard if you think about it. I'll leave it to the student. email me when you think you have the answer.
There is a FPGA company called Siliconblue Technologies that is relatively new and hopefully doing well. I have designed their devices into several products. No earth shattering voodoo in the devices just very low power and very low cost. They also put OTP memory in the device so you don't need a configuration PROM once you are satisfied with your design. Pretty sweet. Tools have been a little cranky but usable, well worth the trouble. firstname.lastname@example.org
oh, this gets better, there's a company called TesseracTech that is touting a 4D FPGA technology.
"TesseracTech is pushing the limits of both physics and credibility with the announcement, which they emphasize is just a technology roadmap - with more details to come as the family gets closer to volume production."
This is akin to a showdown between Dr. Who and his nemesis The Master.
I just took a quick look at the Tabula website, and the first think that struck me about temporal reconfiguration is loss of concurrency and parallelism.
I think its very difficult for an FPGA company to stay afloat, and I think Xilinx is doing an amazing job pushing the envelope with its 6-series and 7-series FPGA processors.
Customers need to also consider including Tablua's FPGA's into their products, and Tablua doesn't have a development kit for the ABAX 3PLD.
I don't see a compelling enough reason to even shift or consider the Tabula FPGAs, and if that's first impressions, then I doubt Tablua would last long, I'd give it 5 years max before the company winds up or gets acquired due to losses, and its IP bought over by a larger company,
I remember the first time I heard about using RAM as logic- I laughed out load (this was before LOL was invented, by the way). I was designing error correction logic for memories at the time, so that might have fueled my initial response. Look where we are today. I guess I was expecting (hoping) the Tabula technology would give me a similar slap on the back of the head once it came out and the implementation and advantages became obvious. I'm still hopeful, but the lack of product details and amount of 'magic' needed by the technology is a worry...
David Patterson, known for his pioneering research that led to RAID, clusters and more, is part of a team at UC Berkeley that recently made its RISC-V processor architecture an open source hardware offering. We talk with Patterson and one of his colleagues behind the effort about the opportunities they see, what new kinds of designs they hope to enable and what it means for today’s commercial processor giants such as Intel, ARM and Imagination Technologies.