It has been a bad few weeks for FPGA startups. Tier Logic and Abound Logic (M2000) closed the doors, both apparently unable to get funding to continue. After some prodding from several high tech journalists, some bloggers, and a slew of calls from investor/wall street types, I started looking into the Tabula FPGA technology.
Below is an excerpt from Mike Dini's most recent newsletter.
It has been a bad few weeks for FPGA startups. Tier Logic and Abound Logic (M2000) closed the doors, both apparently unable to get funding to continue. After some prodding from several high tech journalists, some bloggers, and a slew of calls from investor/wall street types, I started looking into the Tabula FPGA technology. Tabula is yet another FPGA startup. They kind of came out of stealth mode in March’10. Of them all, they are most richly funded, with $106M invested to date. And they need more.
With the possible exception of Mathstar, I have never worked so hard at trying to figure out how a new type of programmable technology works and how it should be applied. Tabula has come out of stealth mode, only to remain stealthy. One mask came off, revealing a different one. There are simply no coherent technical details to be had and Tabula isn't talking. After studying the available documentation, I cannot even determine how many equivalent flip-flops a given Tabula FPGA contains, let alone if the technology is useful. I can give you a range, but no number to within a factor of 8.
Worse, Tabula has no example RTL implementations of, well, anything. The devices appear to be slow, even in the 40nm TSMC process. Also, they appear to be relatively small, maxing out at 1-2M equivalent ASIC gates. This is comparable to Spartan-6 and nowhere near the larger Xilinx Virtex-6 or Altera Stratix-4. Worse, the technology will consume more power due to the massive amounts of context switching involved. The price points presented to us where OK, but not mind blowing.
Regarding the structure, rather than making a two dimensional FPGA as do all other FPGA vendors, Tabula has some magic ‘fold’ that is reconfigured up to 8 times per clock cycle. This mysterious ‘fold’ consists of something less than a 4-input LUT and one, or more, transparent latches. Clearly some routing is thrown into the mix, but how much and its structure is proprietary. The latch holds the interim logic result while the fold and routing are reconfigured. They have added ‘time’ as a third dimension by rapidly reconfiguring the same basic logic block. Frankly, this isn't terribly clever, but they do come up with some cool new Latin-based terms.
The devil here is in the details and implementation. They claim they can do the folding trick with the tools while hiding the details from the FPGA developer. This claim is so silly it makes my teeth itch and represents high-tech marketing at its most repugnant. If my design doesn't meet timing and I know nothing about the underlying architecture, how do I fix my problem? Assume a LARGE amount of technical support will be necessary.
At some point in the life of an FPGA startup, the target of your pitch changes from investors to engineers. Tabula has not yet made that transition. I'm not optimistic about this technology.
Mike Dini is President of The Dini Group (La Jolla, California). To read more of his newsletter click here.