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Embedded processors in FPGAs amplify verification challenges

Dave Orecchio
8/18/2010 06:45 AM EDT

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Dr Marty
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re: Embedded processors in FPGAs amplify verification challenges
Dr Marty   9/9/2010 10:25:42 PM
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I agree with DrDSP. The merging of embedded software and FPGA domains should not automatically increase verification challenges. When debugging an embedded system that uses an OTS processor, we don't try to verify the operation of the silicon. So why do we think we need to verify the operation of IP in an Embedded FPGA system? Sure if you are developing the IP in parallel to the software then it may be necessary to perform some co-verification (of SW and HW) but that should be done at a local level and not at the system level. Once the IP has been appropriately constrained and verified, it should be treated the same as any other piece of hard IP. I think we need to be very careful imposing the verification regimes of traditional FPGA flows into the embedded space.

DrFPGA
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re: Embedded processors in FPGAs amplify verification challenges
DrFPGA   8/31/2010 9:59:18 PM
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I guess a related question is what level of simulation is required for an embedded FPGA. Since it is an FPGA you can just verify the 'logic' to make sure it is working and then use your friendly evaluation board (or a prototype board) to just run the software in real time. Maybe you even use a hardware emulator (remember those?) Are you going to find any 'software' bugs that impact the board level design? Maybe I'm boing old fashioned but one of the advantages of using FPGAs is to get a prototype up and working quickly to iron out those last few bugs instead of spending so much time verifying everything. Is this the wrong approach?

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