KaiSemi performs automated FPGA-to-ASIC conversion with Zero NRE, functional guarantee, and a very short cycle time; this is a full turnkey solution that is seamless to the customer.
A few months ago I penned an article about a new FPGA startup called Tier Logic, which – to my mind – had a really clever FPGA architecture and a REALLY clever FPGA-to-ASIC migration path. Unfortunately Tier Logic is no longer with us, but...
I just received a rather interesting email from Gal Gilat, who is the CEO of KaiSemi (www.kaisemi.com) in Israel. Gal's message certainly caught my attention as follows:
Hello Max, I saw that you were impressed by Tier Logic's FPGA-to-ASIC model. Well, you should look at our offering! We perform automated FPGA-to-ASIC conversion with Zero NRE, functional guarantee, and a very short cycle time. This is a full turnkey solution that is seamless to the customer. We support any FPGA and we also are backed-up by Toshiba. We are using a unique tool that we have developed, converting directly from the FPGA NETLIST (without touching the RTL source) to a gate-level library in one out of five possible processes that are already installed in our database.
Well, you can tickle my toes with a hammer if this doesn’t sound rather interesting. I immediately emailed Gal to find out more. He replied that he's on the road at the moment, but that we can link up for a chat later this week or early next week.
At that time, I shall discover as much as I can and report back ... watch this space!