A few months ago I penned an article about a new FPGA startup called Tier Logic, which – to my mind – had a really clever FPGA architecture and a REALLY clever FPGA-to-ASIC migration path. Unfortunately Tier Logic is no longer with us, but...
I just received a rather interesting email from Gal Gilat, who is the CEO of KaiSemi (www.kaisemi.com) in Israel. Gal's message certainly caught my attention as follows:
Hello Max, I saw that you were impressed by Tier Logic's FPGA-to-ASIC model. Well, you should look at our offering! We perform automated FPGA-to-ASIC conversion with Zero NRE, functional guarantee, and a very short cycle time. This is a full turnkey solution that is seamless to the customer. We support any FPGA and we also are backed-up by Toshiba. We are using a unique tool that we have developed, converting directly from the FPGA NETLIST (without touching the RTL source) to a gate-level library in one out of five possible processes that are already installed in our database.
Well, you can tickle my toes with a hammer if this doesn’t sound rather interesting. I immediately emailed Gal to find out more. He replied that he's on the road at the moment, but that we can link up for a chat later this week or early next week.
At that time, I shall discover as much as I can and report back ... watch this space!
Minimum quantity and price are mainly defined by 2 categories: 1) Targeted die size, and 2) targeted Fab-process. Theses 2 categories are much different from design to design and have great impact on price as well as on minimum quantity.
Therefore, KaiSemi offers a RFQ for a customer to fill, according which KaiSemi performs a quick calculates of die size and required optimized fab-process, and provide a quote for the specific design.
The RFQ consists of 10 simple questions about your FPGA design (as Max Frequency, used LUT amount, etc) that are informed on the FPGA report files.
In order to have a quote, considering min-quantities, please fill the RFQ on this link:
For the given example of VIRTEX-5, depending on its type and size and also design frequncy, minimum quantity is about 1K and up. Nevertheless, for having an accurate answer, you'll need to follow the link and answer those 10 Qs.
Hi regarding (1) timing and (2) RAMs:
1) Timing is closed pretty easy, because FPGAs technology has a huge overhead in timing, because in FPGAs you have huge amount of routing, junctions, fan-out buffers, on the nets and also on the clock tree. When you go to an ASIC hardening the clock tree is dedicated to a design and achieve much better skew. Also the logic area is shrinked by around 90% which ease the timing as well.
2) RAM are replaced according their functional address space and not replaced according block by block. We use RAM compiler of a proven Fab library to create RAMs on standard fab processes. The RAM's sizes are created according the functional size of the used memory.
Regarding Zero NRE, let me try to explain in short:
Zero NRE is doable for 2 reasons:
1. On the business side, the target customers are those who require cost reduction where their quantities pass the breakeven point from which it is worthy to go to an ASIC. Calculating the chip price, we take into account all our one-time expenses and manufacturing expenses amortizing into the chip price. The chip price for the quantities over the minimum, including all the expenses will be cheaper than the FPGA part price. On top of that, we quote 2 prices: 1st year chip cost and 2nd year chip cost. chip cost on the 1st year chip cost need to cover all the one-time expenses (and it is a non cancellation order), and any other order chip cost has to cover just the manufacturing cost. Usually 1st order cost is already 40-50% cheaper, and 2nd order cost is 60-70% cheaper. So you get a cheaper chip with No NRE, based on quantities. And, today, min-quantities are not high.
2. On the technical aspect it stands for backing the functional guarantee that we give meaning paying only after prototypes are approved. The functional guarantee is enabled because there is no RTL touch, no human error on the automated conversion part and vast experience.
David Patterson, known for his pioneering research that led to RAID, clusters and more, is part of a team at UC Berkeley that recently made its RISC-V processor architecture an open source hardware offering. We talk with Patterson and one of his colleagues behind the effort about the opportunities they see, what new kinds of designs they hope to enable and what it means for today’s commercial processor giants such as Intel, ARM and Imagination Technologies.