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Are FPGA tools dumb?

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BrianBailey
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re: Are FPGA tools dumb?
BrianBailey   9/9/2010 9:20:16 PM
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I would agree with that, but I do not want to call out any specific area as being more advantaged than others. I said in a presentation at DAC, that expect the first people to have a fully operable ESL flow would be the platform chip providers, such as Cypress, TI etc. These have constrained architectures which make it easier to put full flows together. Following on their heels will be flows for FPGAs and the finally for full ASICs. This all has to do with the implementation constraints taking away degrees of freedom and making tool creation easier.

BrianBailey
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re: Are FPGA tools dumb?
BrianBailey   9/9/2010 9:17:40 PM
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I am not sure I fully understand the question, but let me try. Every implementation target is going to have a library of devices. For FPGAs these are either built out of the array primitives, or have a number of other larger units integrated onto the fabric. For ASICs there is a lot more variety in the building blocks, their sizes, the power profiles etc. Many of the synthesis tools will automatically do the selection to make the best choices for the optimizations you have requested. I am not sure that people would manually make most of these selections today. Now it is possible that the technology, FAB, and physical libraries used may have been selected because of the availability of certain cells, or general characteristics that are to be taken advantage of with a design, but that is a macro decision and not on a cell basis, or often even on a design basis. That may well be a strategic decision. The only thing I can think you are asking is about the characterization process itself. This will often use simulation at certain operating conditions to extract information such as timing, power etc, or these calculations may be don on the fly with certain synthesis tools.

le_snelson
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re: Are FPGA tools dumb?
le_snelson   9/9/2010 7:10:43 PM
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Several years back I took a VHDL course to facilitate supervising an FPGA based redesign of hardware with a large legacy software suite. The key take-away was the engineer's need to understand the subtle differences in the various vendors' libraries to make the best selection of components and design patterns for the job. What is the state of the art currently w.r.t. the tools' support for comparing component advantages via simulation and verification? Please expand your observations to ASICS and particularly the transition from software algorithm design to FPGA to ASIC.

Max The Magnificent
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re: Are FPGA tools dumb?
Max The Magnificent   9/7/2010 9:19:25 PM
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At the moment I think some of the more interesting EDA tools are appearing in the FPGA arena, especially in the case of creating radiation-tolerant designs. Do you agree ... or not?

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