Breaking News
Blog

Debugging FPGAs at full speed

NO RATINGS
View Comments: Newest First | Oldest First | Threaded View
BrianBailey
User Rank
Blogger
re: Debugging FPGAs at full speed
BrianBailey   9/23/2010 4:25:49 PM
NO RATINGS
I agree that this is not a good technique to find a sub-clock timing problem, it is for functional problems.

ttt3
User Rank
Rookie
re: Debugging FPGAs at full speed
ttt3   9/23/2010 4:10:55 PM
NO RATINGS
While ChipScope/SignalTap are very useful, I've been involved with several FPGA designs where, once one attempts to debug a problem by instrumenting the design using these tools, the problem magically "disappears", likely due to the fact that you had to re-synthesize the design, which "fixed" your marginal timing problem.... until you build 1000 boards and 100 of them don't work due to the marginal timing in the design.

schmalisch
User Rank
Rookie
re: Debugging FPGAs at full speed
schmalisch   9/23/2010 3:38:15 PM
NO RATINGS
Another option is a combination of on-chip instrumentation with a logic analyzer. So it is possible to analyze a longer time frame just depending on the available memory in the logic analyzer. I know that Tektronix and Agilent provide such solutions for Xilinx and Altera FPGAs.

BrianBailey
User Rank
Blogger
re: Debugging FPGAs at full speed
BrianBailey   9/23/2010 3:11:18 PM
NO RATINGS
You are right, that if you are on the limit in terms of timing, then adding any additional logic can have an impact. There are ways to mitigate this for some designs by buffering locally so that long paths are not added to signals, but this adds more area overhead. The only way to 100% non-intrusively do it is through external monitoring - and even this can change timing by adding the probes. While I cannot know your situation specifics, I would look to see if I could slow down the entire application, say 10%, while performing debug, and thus provide a little more timing leeway.

karax
User Rank
Rookie
re: Debugging FPGAs at full speed
karax   9/23/2010 2:29:42 PM
NO RATINGS
Not only affect the RAM resources, these technologies also affects the design timing. That'a very important when you design with high frequency and the synthesis is near of the frequency limit.

Max The Magnificent
User Rank
Blogger
re: Debugging FPGAs at full speed
Max The Magnificent   9/21/2010 3:32:58 PM
NO RATINGS
I think the SignalTap and ChipScope technologies (which I tend to think of as 'virtual logic analyzers') are really clever, but they are limited with regard to the amount of data you can collect because they are consuming on-chip RAM resources.

Flash Poll
Radio
LATEST ARCHIVED BROADCAST
EE Times editor Junko Yoshida grills two executives --Rick Walker, senior product marketing manager for IoT and home automation for CSR, and Jim Reich, CTO and co-founder at Palatehome.
Like Us on Facebook

Datasheets.com Parts Search

185 million searchable parts
(please enter a part number or hit search to begin)
EE Times on Twitter
EE Times Twitter Feed