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Desperately seeking solutions

Lauro Rizzatti
9/21/2010 04:19 PM EDT

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DKC
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re: Desperately seeking solutions
DKC   9/22/2010 8:03:33 PM
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Seems to me that the design methodology is at fault, just making the verification faster doesn't fix that - it will just reduce the time it takes to execute the same old bad practices. Some correct-by-construction tools and formal verification should at least remove the functional verification problem. Verifying your power-management, timing, analog and RF stuff is beyond what an FPGA box will do.

Max The Magnificent
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re: Desperately seeking solutions
Max The Magnificent   9/21/2010 4:37:56 PM
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I would be very interested to see a breakdown of ASIC/SoC Designs showing the distribution of size. Like out of 100 designs how many have 5 million gates or less... how many have 10 million gates... 50 million gates ... 100 million gates ... more than 1 billion gates...

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