Hi Max, Funny you should ask … I had an interesting experience of re-using a prototype board (heavily reliant on Lattice MACH XO CPLDs) from a development project to do a proof of concept for the business development group.
While working in our Medical Group developing a new rapid infusion pump, we needed to build a single large prototype to permit the software team to work on critical code for the micro-controller (RISC Atmel chip). We knew we would need a board stack (one main board plus an HMI board) in the actual unit, but the mechanical constraints were still being worked on, thus the need for the prototype. The design contained one MACH XO CPLD for the “safety” circuitry (in some medical devices, safety cannot be based solely on software) and another MACH XO would handle display and user input. Anyway, this was all spread out on a prototype for ease of development and troubleshooting.
About that time, business development wanted a quick estimate on what it would take in time and effort to redesign an older “build-to-print” centrifuge product that was having issues with obsolescence and procurement of parts. The centrifuge had a few membrane pushbuttons and two, four-digit, 7-segment displays plus a couple of status LEDs on its’ front panel. My infusion pump prototype had plenty of pushbuttons and LEDs and essentially the same pair of 7-segment displays that the centrifuge had (to display elapsed time and RPMs). So, I decided that instead of taking a “blue-sky” guess at the redesign effort, I would just use a few hours designing circuits in the CPLDs of the prototype that would emulate and, therefore, demonstrate the operation of the centrifuge. The MACH XO chips have built-in oscillators that were accurate enough for the timing needed to simulate the centrifuge’ optical encoder input. One chip provided the timed stimulus while the second simulated the actual centrifuge control and display circuits. I put a few adhesive-backed labels on the buttons and displays so the BD guy could “operate” the “centrifuge” in the same fashion that the real product operated. I even had LEDS on the prototype that roughly formed a circle around the 7-segment displays, so I illuminated them in a circular pattern while the “centrifuge” accelerated, ran, then decelerated for its’ expected duration (the actual product had a window so you could see the turntable spin up). The 7-segment displays accurately displayed elapsed time and RPMs like the real unit. Although I used both CPLDs for the demo, one CPLD would do the job in an actual application. That one chip would replace about 15 sq. in’ of circuits that were mostly obsolete. At this point, if we were tasked with the job, 70% of the redesign was already done!
Needless to say, the BD guy was stoked! A demo beats an estimate every time. Best regards, Ken
Hey guys ! i've made an OTN Framer G709 at 2.5 Gig with FEC Correcting Error Algorithme.
This design is based on TDM Time Division Multiplexing.
The principle is to add extra information to a primary Flux as SDH (STM 16) to allow the trame to travel accross an optical fiber.
The FEC allow to correct errors and give you Performence Monitoring QoS Quality of service with correcting errors reporting.
David Patterson, known for his pioneering research that led to RAID, clusters and more, is part of a team at UC Berkeley that recently made its RISC-V processor architecture an open source hardware offering. We talk with Patterson and one of his colleagues behind the effort about the opportunities they see, what new kinds of designs they hope to enable and what it means for today’s commercial processor giants such as Intel, ARM and Imagination Technologies.