Breaking News
Blog

Xilinx multi-FPGA provides mega-boost re capacity, performance, and power efficiency!

Clive Maxfield
10/27/2010 05:36 PM EDT

 17 comments   post a comment
NO RATINGS
View Comments: Newest First | Oldest First | Threaded View
Page 1 / 2   >   >>
paul.dillien
User Rank
Blogger
re: Xilinx multi-FPGA provides mega-boost re capacity, performance, and power efficiency!
paul.dillien   11/1/2010 6:15:41 PM
NO RATINGS
In reply to “goafrit” on the likely selling price of the 2M LUT device, you can figure out a ball-park. I analysed the prices of existing products in my “FPGA Market Report” (a shameless plug...) based on the cost of 1k off 4-input logic elements. Using the largest device currently offered by Xilinx (XC6VLX760-1FF1760C) with a claimed equivalent capacity of 759k LEs and the sample quantity pricing of $15,622, this translates to a price of $20.59 per 1,000 LEs. The proposed XC7V1500T will have have 1,954,560 4-input equivalents. Assuming that the price of the largest 28-nm Virtex-7 device is set, say, at 70% of the existing 40-nm Virtex-6, suggests that the price per 1k LEs would be around $14. Multiplying this price by the capacity suggests a ball-park selling price of around $28,000. That level of pricing would not be an issue for customers, say, who are prototyping ASIC devices. The other way to think about it is that Xilinx has announced a device that is significantly bigger than anything proposed by Altera, and can price accordingly. Perhaps I should not discount the recently announced Achronix device with 2.5 M LE equivalents to use the Intel 22-nm because samples of the first device are promised for Q4 of next year, compared to XC7V1500T in 2H of 2011.

Les_Slater
User Rank
CEO
re: Xilinx multi-FPGA provides mega-boost re capacity, performance, and power efficiency!
Les_Slater   10/30/2010 3:55:52 PM
NO RATINGS
My first experience with Xilinx was in the early stages of the XC2064; I may have gotten some of their first product. My design was a 3-chip CRT controller. The three chips handled I/O for independent CRTs, the timing, memory addressing and I/O and serializing the data into 2-bit pixels for each monitor. All three parts were synchronous from a single clock source. The biggest difficulty was matching propagation delays, never mind min/max. The most difficult was the I/O (remember data was going through the FPGA to the memory, back to the FPGA and serialized out while the RAM addressing was being kept within timing constraints). Like I said I/O timing was the most difficult to accommodate. This was 25 years ago but relatively speaking we have some of the same problems. Back then we had problems that wouldn't fit into a single die; we still do.

_hm
User Rank
CEO
re: Xilinx multi-FPGA provides mega-boost re capacity, performance, and power efficiency!
_hm   10/30/2010 5:38:30 AM
NO RATINGS
This does not look very good implementation. Xilinx tools - ISE and EDK - are not so friendly or stable. This design implemntation will using them more difficult. Also, as new process geometry evolves, this may soon become obsolete. We would also like to know the reliability data from Xilinx.

Max The Magnificent
User Rank
Blogger
re: Xilinx multi-FPGA provides mega-boost re capacity, performance, and power efficiency!
Max The Magnificent   10/29/2010 7:17:39 PM
NO RATINGS
Oh, OK, I can squeeze that in ... thanks for the link -- Ill read it this weekend -- Max

Les_Slater
User Rank
CEO
re: Xilinx multi-FPGA provides mega-boost re capacity, performance, and power efficiency!
Les_Slater   10/29/2010 7:11:40 PM
NO RATINGS
It's fairly short, sixteen pages, and not very technical. A short word of introduction from Warren Weaver: "The word communication will be used here in a very broad sense to include all of the procedures by which one mind may affect another. This, of course, involves not only written and oral speech, but also music, the pictorial arts, the theatre, the ballet, and in fact all human behavior." http://academic.evergreen.edu/a/arunc/compmusic/weaver/weaver.pdf

Max The Magnificent
User Rank
Blogger
re: Xilinx multi-FPGA provides mega-boost re capacity, performance, and power efficiency!
Max The Magnificent   10/29/2010 6:59:45 PM
NO RATINGS
At the moment I am so back-logged with stuff to read that I cannot think of adding anything else to the pile (my head hurts :-)

Les_Slater
User Rank
CEO
re: Xilinx multi-FPGA provides mega-boost re capacity, performance, and power efficiency!
Les_Slater   10/29/2010 6:35:00 PM
NO RATINGS
Max, it might be useful to re-read Warren Weaver's introduction to the '63 edition of Claude Shannon's 'A Mathematical Theory of Communication'.

Max The Magnificent
User Rank
Blogger
re: Xilinx multi-FPGA provides mega-boost re capacity, performance, and power efficiency!
Max The Magnificent   10/29/2010 4:04:45 PM
NO RATINGS
There are many reasons why English isn't consistent -- I'm actually planning on writing a series of articles on English (grammar, history, other stuff) explaining things like how to set about writing articles and papers and suchlike -- I'm hoping it will be a lot more interesting than it sounds here (grin) -- I'll try to post the first one next week -- Max

Les_Slater
User Rank
CEO
re: Xilinx multi-FPGA provides mega-boost re capacity, performance, and power efficiency!
Les_Slater   10/29/2010 3:13:18 PM
NO RATINGS
Thanks Max, I dropped out of high school because I was flunking English and wouldn't have had enough credits to graduate anyway. English usage is not always consistent and that's true in the technical realm also. Also 'dice' as plural for 'die' grates on me. Hope nobody's loosing any sleep over this. For a tendency to shudder over trivia, see a physician.

Max The Magnificent
User Rank
Blogger
re: Xilinx multi-FPGA provides mega-boost re capacity, performance, and power efficiency!
Max The Magnificent   10/29/2010 1:33:43 PM
NO RATINGS
What do any of us know? Why is the plural of herring herring? If you look at the Wikipedia is says: "The wafer is then cut into rectangular blocks, each of which is called a die. Each good die (plural dice, dies, or die) is then..." If you visit Dictionary.com the plural is *dies* with regard to machinery or an engraving stamp and *dice* with regard to architecture (also *dice* with regard to the small cubes with numbers used in board games). This a tricky one -- I know what you mean when you say it brings you to a shuddering halt -- there are other things that do the same to me -- but I think it's what you are used to -- when I was new to the industry I was told that the plural of die was die (in the context of unpackaged silicon chips) and it sort of stuck -- sorry :-)

Page 1 / 2   >   >>
Flash Poll
Radio
LATEST ARCHIVED BROADCAST
Join our online Radio Show on Friday 11th July starting at 2:00pm Eastern, when EETimes editor of all things fun and interesting, Max Maxfield, and embedded systems expert, Jack Ganssle, will debate as to just what is, and is not, and embedded system.
Like Us on Facebook

Datasheets.com Parts Search

185 million searchable parts
(please enter a part number or hit search to begin)
EE Times on Twitter
EE Times Twitter Feed
Top Comments of the Week