Quite apart from anything else, the conference is to be co-chaired between yours truly and Dylan McGrath, who is the editor of EETimes.com (Click Here for more information and to register).
This is going to be a really cool conference. For example, our keynote address will be given by a person I personally hold in great regard – Steve Teig – who is the president and chief technology officer of Tabula and the inventor of Tabula’s Spacetime three-dimensional programmable logic architecture.
Steve is an “Engineer’s Engineer.” In 2002, for example, he broke Thomas Edison’s record for the number of patents filed by an individual in a single year! In his presentation, Steve will be explaining why he thinks our modern computing model is broken and how a new abstraction for computing will be needed to fix it.
In addition to this “must see” keynote, throughout the course of the day we’ll be offering a series of compelling and informative presentations (with expert panelists and Q&A sessions in which you can participate) on topics ranging from system-level design, to IP selection and management, to system-level verification. Also, you’ll be able to join in ad-hoc and scheduled conversations on a range of topics -- you can check the listings in the auditorium for the full schedule; meanwhile, the descriptions of the three main panel sessions are as follows:
In today's environment, the ROI of each SoC design must be carefully considered. Many designs (and companies) have failed they weren't targeted at sufficiently high-volume applications or they were developed using inefficient or costly technology. Success also requires creating a differentiated product. This session will consider the variety of system-level design and automation tools that are available to improve productivity and quality. Also considered will be the tool systems and usage models required to allow all parts of the system-design process to work together in a flexible and constructive way.IP and IP Selection
The choices for both sources and types of IP are extensive and can be quite confusing. There are numerous options for soft processor cores, IP blocks targeting signal processing, digital peripherals, communication functions, as well as hardware acceleration of algorithms. In this session, a diverse panel of industry experts will discuss the selection of products that can both simplify the implementation of these functions and significantly lower their system and energy costs.System-Level Verification
Verification is the single biggest challenge in the design of SoC devices and reusable IP blocks. There is a tremendous variety of software and hardware-assisted verification technologies available, but which will be the most effective for a particular project? What special verification tools and flows are available for ASIC and FPGA-based SoCs? Can point tools address any "EDA holes" in the large ASIC- and FPGA-based SoC design flows? Architecture-related verification, RTL debug, formal verification, and hardware-assisted verification technologies will all be considered in this session.
In addition to moderating the System Level Design and System Level Verification panels, I'll also be hosting one of the online chat sessions titled "Glass half full? Biggest SoC Design Successes"
where we can all tell tall tales of the designs we've been involved in. So, I very much look forward to seeing you there.