The electronics industry is a dog with two heads. One is the market pull created by the expectations of the end user—us consumers of technology—for ever higher performance products. The other head is the technology push of lithography technology to enable acceptable profit for ever smaller channel length transistors. This is the engine that has driven Moore’s Law for the last 50 years.
The rest of the electronics industry is the tail wagged by these two heads. This market pull and technology push has shaped the electronics industry food chain.
Shorter transistor features mean faster switching and higher bandwidth signals, introducing signal integrity concerns into more and more products. Smaller transistors mean higher gate density which drives more I/O requiring higher interconnect density hardware, with the manufacturing and design infrastructure to support it.
Every aspect of the electronics industry is wagged by these two heads, all the way down to the printed circuit board. This was evident to me when I spent an afternoon with George Dudnikov, Sr. VP and CTO of the PCB and Backplane Divisions of Sanmina-SCI, a leader in printed circuit board technology. He walked me through some of the requirements for high end circuit boards and the technology solutions currently and soon to be introduced into high volume production.
Sanmina-SCI is a vertically integrated EMS company. Their Interconnect Technology Systems Division focuses on high end boards and backplanes, with an average of 18 layers and all the way up to 60 layers, some up to 500 mils thick. They have been shipping volume applications operating with 10 Gbps channels for more than five years. While prototypes have been built operating at 25 Gbps, Dudnikov says the limitation to volume expansion is limited by transceiver availability.
He points out that even when a specific backplane application may only be 5 or 6 Gbps, customers often want scalability built into the hardware. After all, every high speed serial protocol has a roadmap leading toward ever higher data rates per channel. Once a backplane is embedded in a system in the field, replacing a line card can instantly upgrade the system to the next generation, as long as the backplane can support the higher data rates.
In this regime of interconnect length and data rates, signal integrity effects are a dominant driver for performance. “Designing Transparent Interconnects™ is our goal, to be the invisible interconnect. This is the way we think,” Dudnikov says.
To meet these requirements, Sanmina-SCI has developed and introduced a number of new technologies for high volume production. “We are giving our customers a tool box of options, and most of our proprietary technologies are available for licensing,” Dudnikov said.
Buried capacitance, or BC, layers have been used in production for more than 15 years. Fundamentally, they are dielectric layers, 2 mils or thinner, used between the power and ground planes. While their name suggests their advantage as added capacitance, Dudnikov is the first to point out their real advantage is all about the lower spreading inductance the thin laminate offers for power distribution applications. Buried capacitance cores down to 8 microns thick are currently in available. With the addition of nanopowders to the dielectric, Dudnikov says the capacitance per area is increased to 40-80 nF/square inch, about 100x higher than a conventional 3 mil thick FR4 layer.
Very interesting, almost shocking ;-), embedded ESD protection by Shocking Technologies...although I was a little puzzled by the wording in the artcile: "plans to solve"...is this for real? has anyone beyond Sanmina's trying to accomplish this feat with this "switchable dielectric material"...Kris
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